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Searched refs:sxtb16 (Results 1 – 25 of 32) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dthumb2-dsp-diag.s7 sxtb16 r0, r0 label
8 sxtb16 r0, r0, ror #8 label
17 @ CHECK-7EM: sxtb16 r0, r0 @ encoding: [0x2f,0xfa,0x80,0xf0]
18 @ CHECK-7EM: sxtb16 r0, r0, ror #8 @ encoding: [0x2f,0xfa,0x90,0xf0]
Dbasic-thumb2-instructions.s3207 sxtb16 r1, r4
3208 sxtb16 r6, r7, ror #0
3209 sxtb16 r3, r1, ror #16
3214 @ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1]
3215 @ CHECK: sxtb16 r6, r7 @ encoding: [0x2f,0xfa,0x87,0xf6]
3216 @ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x2f,0xfa,0xa1,0xf3]
3263 sxtb16 r1, r4
3264 sxtb16 r6, r7, ror #0
3265 sxtb16 r3, r1, ror #16
3270 @ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1]
[all …]
Dbasic-arm-instructions.s3093 sxtb16 r1, r4
3094 sxtb16 r6, r7, ror #0
3096 sxtb16 r3, r1, ror #16
3099 @ CHECK: sxtb16 r1, r4 @ encoding: [0x74,0x10,0x8f,0xe6]
3100 @ CHECK: sxtb16 r6, r7 @ encoding: [0x77,0x60,0x8f,0xe6]
3102 @ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x71,0x38,0x8f,0xe6]
/external/llvm/test/MC/ARM/
Dthumb2-dsp-diag.s7 sxtb16 r0, r0 label
8 sxtb16 r0, r0, ror #8 label
17 @ CHECK-7EM: sxtb16 r0, r0 @ encoding: [0x2f,0xfa,0x80,0xf0]
18 @ CHECK-7EM: sxtb16 r0, r0, ror #8 @ encoding: [0x2f,0xfa,0x90,0xf0]
Dbasic-thumb2-instructions.s3151 sxtb16 r1, r4
3152 sxtb16 r6, r7, ror #0
3153 sxtb16 r3, r1, ror #16
3158 @ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1]
3159 @ CHECK: sxtb16 r6, r7 @ encoding: [0x2f,0xfa,0x87,0xf6]
3160 @ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x2f,0xfa,0xa1,0xf3]
3207 sxtb16 r1, r4
3208 sxtb16 r6, r7, ror #0
3209 sxtb16 r3, r1, ror #16
3214 @ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1]
[all …]
Dbasic-arm-instructions.s3091 sxtb16 r1, r4
3092 sxtb16 r6, r7, ror #0
3094 sxtb16 r3, r1, ror #16
3097 @ CHECK: sxtb16 r1, r4 @ encoding: [0x74,0x10,0x8f,0xe6]
3098 @ CHECK: sxtb16 r6, r7 @ encoding: [0x77,0x60,0x8f,0xe6]
3100 @ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x71,0x38,0x8f,0xe6]
/external/llvm/test/MC/Disassembler/ARM/
Dunpredictable-AExtI-arm.txt26 # CHECK: sxtb16
Dthumb2.txt2177 # CHECK: sxtb16 r1, r4
2178 # CHECK: sxtb16 r6, r7
2179 # CHECK: sxtb16 r3, r1, ror #16
2231 # CHECK: sxtb16 r1, r4
2232 # CHECK: sxtb16 r6, r7
2233 # CHECK: sxtb16 r3, r1, ror #16
Dbasic-arm-instructions.txt2107 # CHECK: sxtb16 r1, r4
2108 # CHECK: sxtb16 r6, r7
2110 # CHECK: sxtb16 r3, r1, ror #16
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dunpredictable-AExtI-arm.txt26 # CHECK: sxtb16
Dthumb2.txt2177 # CHECK: sxtb16 r1, r4
2178 # CHECK: sxtb16 r6, r7
2179 # CHECK: sxtb16 r3, r1, ror #16
2231 # CHECK: sxtb16 r1, r4
2232 # CHECK: sxtb16 r6, r7
2233 # CHECK: sxtb16 r3, r1, ror #16
Dbasic-arm-instructions.txt2107 # CHECK: sxtb16 r1, r4
2108 # CHECK: sxtb16 r6, r7
2110 # CHECK: sxtb16 r3, r1, ror #16
/external/capstone/suite/MC/ARM/
Dbasic-thumb2-instructions.s.cs1020 0x2f,0xfa,0x84,0xf1 = sxtb16 r1, r4
1021 0x2f,0xfa,0x87,0xf6 = sxtb16 r6, r7
1022 0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #16
1039 0x2f,0xfa,0x84,0xf1 = sxtb16 r1, r4
1040 0x2f,0xfa,0x87,0xf6 = sxtb16 r6, r7
1041 0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #16
Dbasic-arm-instructions.s.cs867 0x74,0x10,0x8f,0xe6 = sxtb16 r1, r4
868 0x77,0x60,0x8f,0xe6 = sxtb16 r6, r7
870 0x71,0x38,0x8f,0xe6 = sxtb16 r3, r1, ror #16
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dacle-intrinsics.ll62 ; CHECK: sxtb16 r0, r0
66 %tmp1 = call i32 @llvm.arm.sxtb16(i32 %tmp)
428 declare i32 @llvm.arm.sxtb16(i32)
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-operand-rn-t32.cc61 M(sxtb16) \
Dtest-assembler-cond-rd-operand-rn-a32.cc61 M(sxtb16) \
Dtest-assembler-cond-rd-operand-rn-ror-amount-t32.cc53 M(sxtb16) \
Dtest-assembler-cond-rd-operand-rn-ror-amount-a32.cc53 M(sxtb16) \
/external/vixl/src/aarch32/
Dassembler-aarch32.h3577 void sxtb16(Condition cond, Register rd, const Operand& operand);
3578 void sxtb16(Register rd, const Operand& operand) { sxtb16(al, rd, operand); } in sxtb16() function
Ddisasm-aarch32.h1342 void sxtb16(Condition cond, Register rd, const Operand& operand);
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td1975 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
4680 def : InstAlias<"sxtb16${p} $Rd, $Rm",
4726 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td1980 def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">;
4680 def : InstAlias<"sxtb16${p} $Rd, $Rm",
4726 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7764 "xtab\007sxtab16\005sxtah\004sxtb\006sxtb16\004sxth\003tbb\003tbh\003teq"
8984 …{ 1482 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP…
8985 …{ 1482 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, {…
8986 …{ 1482 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDS…
8987 …{ 1482 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDS…
8988 …{ 1482 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|F…
12211 { Feature_HasDSP|Feature_IsThumb2, 1482 /* sxtb16 */, MCK_RotImm, 8 /* 3 */ },
12212 { Feature_HasDSP|Feature_IsThumb2, 1482 /* sxtb16 */, MCK_RotImm, 8 /* 3 */ },
12213 { Feature_IsARM|Feature_HasV6, 1482 /* sxtb16 */, MCK_RotImm, 8 /* 3 */ },
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc9187 AsmString = "sxtb16$\xFF\x04\x01} $\x01, $\x02";
11444 AsmString = "sxtb16$\xFF\x04\x01} $\x01, $\x02";
11453 AsmString = "sxtb16$\xFF\x04\x01} $\x01, $\x02$\xFF\x03\x10";

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