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Searched refs:tc_compatible_htile (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_texture.c47 bool tc_compatible_htile);
220 bool tc_compatible_htile) in si_init_surface() argument
243 } else if (tc_compatible_htile && in si_init_surface()
525 tex->tc_compatible_htile = new_tex->tc_compatible_htile; in si_reallocate_texture_inplace()
919 tex->tc_compatible_htile); in si_print_texture_info()
1009 tex->tc_compatible_htile = sscreen->info.chip_class == GFX8 && in si_texture_create_object()
1101 if (sscreen->info.chip_class >= GFX9 || tex->tc_compatible_htile) in si_texture_create_object()
1229 bool tc_compatible_htile) in si_choose_tiling() argument
1247 if (sscreen->info.chip_class == GFX8 && tc_compatible_htile) in si_choose_tiling()
1311 bool tc_compatible_htile = in si_texture_create() local
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Dsi_clear.c579 !zstex->tc_compatible_htile && in si_clear()
587 zstex->tc_compatible_htile = true; in si_clear()
616 (!zstex->tc_compatible_htile || depth == 0 || depth == 1)) { in si_clear()
641 (!zstex->tc_compatible_htile || stencil == 0)) { in si_clear()
Dsi_pipe.h344 bool tc_compatible_htile : 1; member
1776 assert(!tex->tc_compatible_htile || tex->surface.htile_offset); in vi_tc_compat_htile_enabled()
1777 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask); in vi_tc_compat_htile_enabled()
Dsi_state.c3185 if (!tex->surface.has_stencil && !tex->tc_compatible_htile) { in si_emit_framebuffer_state()
3193 if (tex->tc_compatible_htile) { in si_emit_framebuffer_state()
3210 S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile)); in si_emit_framebuffer_state()
/external/mesa3d/src/amd/vulkan/
Dradv_private.h1878 bool tc_compatible_htile; member
2004 return radv_image_has_htile(image) && image->tc_compatible_htile; in radv_image_is_tc_compat_htile()
Dradv_image.c1312 image->tc_compatible_cmask = image->tc_compatible_htile = 0; in radv_image_reset_layout()
1383 image->tc_compatible_htile = radv_image_has_htile(image) && in radv_image_create_layout()
/external/mesa3d/docs/relnotes/
D20.2.0.rst3209 - radeonsi: allow tc_compatible_htile to be mutable