Searched refs:tcc_cache_line_size (Results 1 – 12 of 12) sorted by relevance
| /external/mesa3d/src/amd/common/ |
| D | ac_gpu_info.h | 104 uint32_t tcc_cache_line_size; member
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| D | ac_gpu_info.c | 559 info->tcc_cache_line_size = 128; in ac_query_gpu_info()
568 info->tcc_cache_line_size = 64; in ac_query_gpu_info()
721 ib_align = MAX2(ib_align, info->tcc_cache_line_size); in ac_query_gpu_info()
914 fprintf(f, " tcc_cache_line_size = %u\n", info->tcc_cache_line_size); in ac_print_gpu_info()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_pipe.h | 1690 unsigned alignment, tcc_cache_line_size; in si_optimal_tcc_alignment() local
1698 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size; in si_optimal_tcc_alignment()
1699 return MIN2(alignment, tcc_cache_line_size); in si_optimal_tcc_alignment()
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| D | si_pipe.c | 639 sscreen->info.tcc_cache_line_size); in si_create_context()
649 sscreen->info.tcc_cache_line_size); in si_create_context()
662 sctx->screen->info.tcc_cache_line_size); in si_create_context()
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| D | si_compute_prim_discard.c | 952 align(out_indexbuf_size, sctx->screen->info.tcc_cache_line_size) <= in si_check_ring_space()
1249 output_indexbuf_size = align(output_indexbuf_size, sctx->screen->info.tcc_cache_line_size); in si_dispatch_prim_discard_cs_and_draw()
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| D | si_buffer.c | 465 sctx->screen->info.tcc_cache_line_size, &offset, in si_buffer_transfer_map()
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| D | si_compute.c | 662 sctx->screen->info.tcc_cache_line_size, &kernel_args_offset, in si_upload_compute_input()
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| D | si_texture.c | 1176 sscreen->info.tcc_cache_line_size); in si_texture_create_object()
1180 sscreen->info.tcc_cache_line_size); in si_texture_create_object()
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| D | si_state_draw.c | 1901 sctx->screen->info.tcc_cache_line_size, in si_multi_draw_vbo()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_pipe_common.c | 163 rctx->screen->info.tcc_cache_line_size, in r600_draw_rectangle()
1337 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size); in r600_common_screen_init()
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| D | r600_buffer_common.c | 419 rctx->screen->info.tcc_cache_line_size, in r600_buffer_transfer_map()
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_winsys.c | 575 ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ in do_winsys_init()
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