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/external/python/cpython3/Lib/test/
Dtest_tcl.py26 tcl = Tcl()
27 patchlevel = tcl.call('info', 'patchlevel')
53 tcl = self.interp
54 tcl.eval('set a 1')
55 self.assertEqual(tcl.eval('set a'),'1')
58 tcl = self.interp
59 self.assertEqual(tcl.eval('set a "a\\0b"'), 'a\x00b')
62 tcl = self.interp
63 self.assertRaises(TclError,tcl.eval,'set a')
66 tcl = self.interp
[all …]
/external/python/cpython2/Lib/test/
Dtest_tcl.py26 tcl = Tcl()
27 patchlevel = tcl.call('info', 'patchlevel')
53 tcl = self.interp
54 tcl.eval('set a 1')
55 self.assertEqual(tcl.eval('set a'),'1')
58 tcl = self.interp
59 self.assertRaises(TclError,tcl.eval,'set a')
62 tcl = self.interp
63 self.assertRaises(TclError,tcl.eval,'this is wrong')
66 tcl = self.interp
[all …]
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_cmdbuf.c75 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl ); in r200SetUpAtomList()
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); in r200FireEB()
154 rmesa->radeon.tcl.elt_dma_bo, in r200FireEB()
163 int nr, elt_used = rmesa->tcl.elt_used; in r200FlushElts()
165 …radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x %d\n", __func__, rmesa->tcl.hw_primitive, elt_u… in r200FlushElts()
172 radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); in r200FlushElts()
174 r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive); in r200FlushElts()
176 radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo); in r200FlushElts()
177 rmesa->radeon.tcl.elt_dma_bo = NULL; in r200FlushElts()
196 radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo, in r200AllocEltsOpenEnded()
[all …]
Dr200_state.c393 R200_STATECHANGE(rmesa, tcl); in r200Fogfv()
394 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK; in r200Fogfv()
397 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_LINEAR; in r200Fogfv()
408 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP; in r200Fogfv()
413 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP2; in r200Fogfv()
499 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL]; in r200CullFace()
526 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) { in r200CullFace()
527 R200_STATECHANGE(rmesa, tcl ); in r200CullFace()
528 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t; in r200CullFace()
540 R200_STATECHANGE( rmesa, tcl ); in r200FrontFace()
[all …]
Dr200_maos_arrays.c115 if (!rmesa->radeon.tcl.aos[i].bo) { in r200EmitArrays()
118 &(rmesa->radeon.tcl.aos[nr]), in r200EmitArrays()
125 &(rmesa->radeon.tcl.aos[nr]), in r200EmitArrays()
174 if (!rmesa->radeon.tcl.aos[nr].bo) { in r200EmitArrays()
176 &(rmesa->radeon.tcl.aos[nr]), in r200EmitArrays()
195 rmesa->radeon.tcl.aos_count = nr; in r200EmitArrays()
Dr200_tcl.c144 rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { in r200AllocElts()
146 GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr + in r200AllocElts()
147 rmesa->radeon.tcl.elt_dma_offset + rmesa->tcl.elt_used); in r200AllocElts()
149 rmesa->tcl.elt_used += nr*2; in r200AllocElts()
158 rmesa->radeon.tcl.aos_count, 0 ); in r200AllocElts()
160 r200EmitMaxVtxIndex(rmesa, rmesa->radeon.tcl.aos[0].count); in r200AllocElts()
161 return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr ); in r200AllocElts()
189 rmesa->radeon.tcl.aos_count, in r200EmitPrim()
195 rmesa->tcl.hw_primitive, in r200EmitPrim()
212 rmesa->tcl.hw_primitive == (PRIM| \
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/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_ioctl.c74 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl); in radeonSetUpAtomList()
171 uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start); in radeonFlushElts()
180 nr = rmesa->tcl.elt_used; in radeonFlushElts()
230 rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; in radeonAllocEltsOpenEnded()
257 rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw; in radeonAllocEltsOpenEnded()
258 rmesa->tcl.elt_used = min_nr; in radeonAllocEltsOpenEnded()
260 retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset); in radeonAllocEltsOpenEnded()
305 rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo; in radeonEmitAOS()
307 (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4); in radeonEmitAOS()
308 rmesa->ioctl.vertex_max = rmesa->radeon.tcl.aos[0].count; in radeonEmitAOS()
[all …]
Dradeon_maos_arrays.c158 if (!rmesa->tcl.obj.buf) in radeonEmitArrays()
160 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
178 if (!rmesa->tcl.norm.buf) in radeonEmitArrays()
180 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
204 if (!rmesa->tcl.rgba.buf) in radeonEmitArrays()
206 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
217 if (!rmesa->tcl.spec.buf) { in radeonEmitArrays()
220 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
235 if (!rmesa->tcl.fog.buf) in radeonEmitArrays()
237 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
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Dradeon_maos_verts.c316 GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & in radeonEmitArrays()
367 if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) { in radeonEmitArrays()
368 RADEON_STATECHANGE( rmesa, tcl ); in radeonEmitArrays()
369 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx; in radeonEmitArrays()
376 if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && in radeonEmitArrays()
377 rmesa->radeon.tcl.aos[0].bo) in radeonEmitArrays()
380 if (rmesa->radeon.tcl.aos[0].bo) in radeonEmitArrays()
384 &rmesa->radeon.tcl.aos[0].bo, in radeonEmitArrays()
385 &rmesa->radeon.tcl.aos[0].offset, in radeonEmitArrays()
397 _math_trans_4f( rmesa->tcl.ObjClean.data, in radeonEmitArrays()
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Dradeon_state.c326 RADEON_STATECHANGE(rmesa, tcl); in radeonFogfv()
327 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK; in radeonFogfv()
330 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR; in radeonFogfv()
333 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP; in radeonFogfv()
336 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2; in radeonFogfv()
405 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL]; in radeonCullFace()
432 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) { in radeonCullFace()
433 RADEON_STATECHANGE(rmesa, tcl ); in radeonCullFace()
434 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t; in radeonCullFace()
446 RADEON_STATECHANGE( rmesa, tcl ); in radeonFrontFace()
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Dradeon_tcl.c115 #define GET_MESA_ELTS() rmesa->tcl.Elts
154 rmesa->radeon.tcl.aos_count, 0 ); in radeonAllocElts()
156 return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format, in radeonAllocElts()
157 rmesa->tcl.hw_primitive, nr ); in radeonAllocElts()
178 rmesa->radeon.tcl.aos_count, in radeonEmitPrim()
184 rmesa->tcl.vertex_format, in radeonEmitPrim()
185 rmesa->tcl.hw_primitive, in radeonEmitPrim()
203 rmesa->tcl.hw_primitive == (PRIM| \
260 if (newprim != rmesa->tcl.hw_primitive || in radeonTclPrimitive()
263 rmesa->tcl.hw_primitive = newprim; in radeonTclPrimitive()
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/external/python/cpython2/Lib/lib-tk/test/test_tkinter/
Dtest_loadtk.py13 tcl = Tcl()
14 self.assertRaises(TclError,tcl.winfo_geometry)
15 tcl.loadtk()
16 self.assertEqual('1x1+0+0', tcl.winfo_geometry())
17 tcl.destroy()
38 tcl = Tcl()
39 self.assertRaises(TclError, tcl.winfo_geometry)
40 self.assertRaises(TclError, tcl.loadtk)
/external/python/cpython3/Lib/tkinter/test/test_tkinter/
Dtest_loadtk.py13 tcl = Tcl()
14 self.assertRaises(TclError,tcl.winfo_geometry)
15 tcl.loadtk()
16 self.assertEqual('1x1+0+0', tcl.winfo_geometry())
17 tcl.destroy()
39 tcl = Tcl()
40 self.assertRaises(TclError, tcl.winfo_geometry)
41 self.assertRaises(TclError, tcl.loadtk)
/external/google-breakpad/src/third_party/libdisasm/swig/
DMakefile16 dummy: swig swig-python swig-ruby swig-perl swig-tcl install uninstall clean
30 swig-tcl:
31 cd tcl && make -f Makefile-swig
46 install-tcl:
47 cd tcl && sudo make -f Makefile-swig install
62 uninstall-tcl:
63 cd tcl && sudo make -f Makefile-swig uninstall
70 cd tcl && make -f Makefile-swig clean
/external/google-breakpad/src/third_party/libdisasm/swig/tcl/
DMakefile-swig27 TCL_MOD = $(BASE_NAME)-tcl.so
30 TCL_INC = /usr/include/tcl$(TCL_VERSION)
31 TCL_LIB = /usr/lib/tcl$(TCL_VERSION)
37 all: swig-tcl
39 dummy: swig-tcl install uninstall clean
41 swig-tcl: $(TCL_MOD)
50 swig -tcl -o $(TCL_SHADOW) -outdir . $<
/external/python/cpython3/Lib/idlelib/idle_test/
Dtest_browser.py89 tcl = list(transform(mock_pyclbr_tree, 'test'))
90 eq(tcl, [C0, f0])
91 eq(tcl[0].name, 'C0(base)')
92 eq(tcl[1].name, 'f0')
94 tcl = list(transform(mock_pyclbr_tree, 'test'))
95 eq(tcl[0].name, 'C0(base)')
97 tcl = list(transform(mock_pyclbr_tree, 'different name'))
98 eq(tcl, [])
104 tcl = list(transform(C0.children))
105 eq(tcl, [F1, C1])
[all …]
/external/python/cpython2/Doc/library/
Dtix.rst82 have a file called :file:`pkgIndex.tcl` (case sensitive), which contains the
112 .. \ulink{Balloon}{http://tix.sourceforge.net/dist/current/demos/samples/Balloon.tcl}
122 .. \ulink{ButtonBox}{http://tix.sourceforge.net/dist/current/demos/samples/BtnBox.tcl}
134 .. \ulink{ComboBox}{http://tix.sourceforge.net/dist/current/demos/samples/ComboBox.tcl}
147 .. \ulink{Control}{http://tix.sourceforge.net/dist/current/demos/samples/Control.tcl}
158 .. \ulink{LabelEntry}{http://tix.sourceforge.net/dist/current/demos/samples/LabEntry.tcl}
170 .. \ulink{LabelFrame}{http://tix.sourceforge.net/dist/current/demos/samples/LabFrame.tcl}
181 .. \ulink{Meter}{http://tix.sourceforge.net/dist/current/demos/samples/Meter.tcl}
191 .. \ulink{OptionMenu}{http://tix.sourceforge.net/dist/current/demos/samples/OptMenu.tcl}
203 .. \ulink{PopupMenu}{http://tix.sourceforge.net/dist/current/demos/samples/PopMenu.tcl}
[all …]
/external/python/cpython3/Doc/library/
Dtkinter.tix.rst100 .. \ulink{Balloon}{http://tix.sourceforge.net/dist/current/demos/samples/Balloon.tcl}
110 .. \ulink{ButtonBox}{http://tix.sourceforge.net/dist/current/demos/samples/BtnBox.tcl}
122 .. \ulink{ComboBox}{http://tix.sourceforge.net/dist/current/demos/samples/ComboBox.tcl}
135 .. \ulink{Control}{http://tix.sourceforge.net/dist/current/demos/samples/Control.tcl}
146 .. \ulink{LabelEntry}{http://tix.sourceforge.net/dist/current/demos/samples/LabEntry.tcl}
158 .. \ulink{LabelFrame}{http://tix.sourceforge.net/dist/current/demos/samples/LabFrame.tcl}
169 .. \ulink{Meter}{http://tix.sourceforge.net/dist/current/demos/samples/Meter.tcl}
179 .. \ulink{OptionMenu}{http://tix.sourceforge.net/dist/current/demos/samples/OptMenu.tcl}
191 .. \ulink{PopupMenu}{http://tix.sourceforge.net/dist/current/demos/samples/PopMenu.tcl}
202 .. \ulink{Select}{http://tix.sourceforge.net/dist/current/demos/samples/Select.tcl}
[all …]
/external/python/cpython2/PC/VC6/
Dbuild_tkinter.py32 tcl = have_args("tcl")
35 if not(tcl) and not(tk) and not(tix):
36 tcl = tk = tix = True
43 if tcl:
Dtcl852.patch1 --- tcl8.5.2\generic\tcl.h Fri Jun 13 03:35:39 2008
2 +++ tcl8.5.2\generic\tcl.h Sun Jan 4 16:52:30 2009
/external/u-boot/arch/arm/mach-sunxi/dram_timings/
Dh6_ddr3_1333.c78 u8 tcl = 6; /* JEDEC: CL / 2 => 6 */ in mctl_set_timing_params() local
91 if (tcl + 1 >= trtp + trp) in mctl_set_timing_params()
92 trtp = tcl + 2 - trp; in mctl_set_timing_params()
102 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_params()
134 writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000, in mctl_set_timing_params()
Dh6_lpddr3.c64 u8 tcl = 5; /* CL 10 */ in mctl_set_timing_params() local
80 u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1; in mctl_set_timing_params()
90 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_params()
122 writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000, in mctl_set_timing_params()
Dlpddr3_stock.c33 u8 tcl = 6; /* CL 12 */ in mctl_set_timing_params() local
45 u8 trd2wr = tcl + 4 + 5 - tcwl + 1; in mctl_set_timing_params()
58 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
/external/clang/test/Modules/
Ddarwin_specific_modulemap_hacks.m12 #error tcl-private/header.h should be textual
16 #import <tcl-private/header.h>
21 #error tcl-private/header.h missing
/external/eigen/cmake/
DEigenConfigureTesting.cmake17 # This call activates testing and generates the DartConfiguration.tcl
22 # Overwrite default DartConfiguration.tcl such that ctest can build our unit tests.
25 file(READ "${CMAKE_CURRENT_BINARY_DIR}/DartConfiguration.tcl" EIGEN_DART_CONFIG_FILE)
33 file(WRITE "${CMAKE_CURRENT_BINARY_DIR}/DartConfiguration.tcl" ${EIGEN_DART_CONFIG_FILE2})

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