Searched refs:timing_data (Results 1 – 9 of 9) sorted by relevance
| /external/u-boot/drivers/ddr/marvell/a38x/ |
| D | mv_ddr_spd.c | 58 int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]) in mv_ddr_spd_timing_calc() argument
67 timing_data[MV_DDR_TCK_AVG_MIN] = calc_val; in mv_ddr_spd_timing_calc()
74 timing_data[MV_DDR_TAA_MIN] = calc_val; in mv_ddr_spd_timing_calc()
77 timing_data[MV_DDR_TRFC1_MIN] = (spd_data->byte_fields.byte_30 + in mv_ddr_spd_timing_calc()
81 timing_data[MV_DDR_TWR_MIN] = (spd_data->byte_fields.byte_42 + in mv_ddr_spd_timing_calc()
90 timing_data[MV_DDR_TRCD_MIN] = calc_val; in mv_ddr_spd_timing_calc()
97 timing_data[MV_DDR_TRP_MIN] = calc_val; in mv_ddr_spd_timing_calc()
106 timing_data[MV_DDR_TRC_MIN] = calc_val; in mv_ddr_spd_timing_calc()
109 timing_data[MV_DDR_TRAS_MIN] = (spd_data->byte_fields.byte_28 + in mv_ddr_spd_timing_calc()
118 timing_data[MV_DDR_TRRD_S_MIN] = calc_val; in mv_ddr_spd_timing_calc()
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| D | mv_ddr_topology.c | 69 if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) { in mv_ddr_topology_map_update()
119 val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk); in mv_ddr_topology_map_update()
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| D | ddr_topology_def.h | 120 unsigned int timing_data[MV_DDR_TDATA_LAST]; member
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| D | mv_ddr_spd.h | 277 int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]);
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| D | ddr3_training.c | 1262 cl_value = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk); in ddr3_tip_freq_set()
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| /external/igt-gpu-tools/tools/ |
| D | intel_vbt_decode.c | 631 const uint8_t *timing_data = lfp_data_ptr + dvo_offset; in dump_lvds_data() local
644 hdisplay = _H_ACTIVE(timing_data); in dump_lvds_data()
645 hsyncstart = hdisplay + _H_SYNC_OFF(timing_data); in dump_lvds_data()
646 hsyncend = hsyncstart + _H_SYNC_WIDTH(timing_data); in dump_lvds_data()
647 htotal = hdisplay + _H_BLANK(timing_data); in dump_lvds_data()
649 vdisplay = _V_ACTIVE(timing_data); in dump_lvds_data()
650 vsyncstart = vdisplay + _V_SYNC_OFF(timing_data); in dump_lvds_data()
651 vsyncend = vsyncstart + _V_SYNC_WIDTH(timing_data); in dump_lvds_data()
652 vtotal = vdisplay + _V_BLANK(timing_data); in dump_lvds_data()
653 clock = _PIXEL_CLOCK(timing_data) / 1000; in dump_lvds_data()
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| /external/u-boot/arch/arm/mach-exynos/ |
| D | clock_init.h | 85 unsigned timing_data; member
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| D | dmc_init_ddr3.c | 129 writel(mem->timing_data, &dmc->timingdata); in ddr3_mem_ctrl_init()
611 writel(mem->timing_data, &drex0->timingdata0); in ddr3_mem_ctrl_init()
612 writel(mem->timing_data, &drex1->timingdata0); in ddr3_mem_ctrl_init()
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| D | clock_init_exynos5.c | 190 .timing_data = 0x3630580b,
293 .timing_data = 0x3630580b,
396 .timing_data = 0x3630580b,
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