Searched refs:tx_burst_size (Results 1 – 4 of 4) sorted by relevance
| /external/u-boot/drivers/ddr/marvell/a38x/ |
| D | ddr3_training_bist.c | 28 u32 tx_burst_size; in ddr3_tip_bist_activate() local
47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
48 pattern_table[pattern].tx_burst_size : 0; in ddr3_tip_bist_activate()
52 pattern_table[pattern].num_of_phases_tx, tx_burst_size, in ddr3_tip_bist_activate()
447 u32 tx_burst_size; in mv_ddr_odpg_bist_prepare() local
469 tx_burst_size = pattern_table[pattern].tx_burst_size; in mv_ddr_odpg_bist_prepare()
473 tx_burst_size = 0; in mv_ddr_odpg_bist_prepare()
478 tx_burst_size, pattern_table[pattern].num_of_phases_rx, burst_delay, in mv_ddr_odpg_bist_prepare()
520 pattern_table[pattern].tx_burst_size, in mv_ddr_dm_vw_get()
553 pattern_table[pattern].tx_burst_size, in mv_ddr_dm_vw_get()
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| D | ddr3_training_ip_engine.c | 350 u32 tx_burst_size; in ddr3_tip_ip_training() local
401 tx_burst_size = (direction == OPER_WRITE) ? in ddr3_tip_ip_training()
402 pattern_table[pattern].tx_burst_size : 0; in ddr3_tip_ip_training()
407 pattern_table[pattern].num_of_phases_tx, tx_burst_size, in ddr3_tip_ip_training()
627 u32 tx_burst_size, u32 rx_phases, in ddr3_tip_configure_odpg() argument
635 (tx_burst_size << 11) | (delay_between_burst << 15) | in ddr3_tip_configure_odpg()
887 (pattern_table[pattern].tx_burst_size << 11) | in ddr3_tip_load_pattern_to_mem()
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| D | ddr3_training_ip.h | 104 u8 tx_burst_size; member
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| D | ddr3_training_ip_flow.h | 109 u32 tx_burst_size, u32 rx_phases,
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