Home
last modified time | relevance | path

Searched refs:tx_ring (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/net/
Deepro100.c197 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ variable
521 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; in eepro100_init()
524 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); in eepro100_init()
534 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); in eepro100_init()
538 !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); in eepro100_init()
546 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { in eepro100_init()
548 le16_to_cpu (tx_ring[tx_cur].status)); in eepro100_init()
557 ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; in eepro100_init()
560 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); in eepro100_init()
571 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); in eepro100_init()
[all …]
Ddc2114x.c136 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring … variable
345 tx_ring[i].status = 0; in dc21x4x_init()
346 tx_ring[i].des1 = 0; in dc21x4x_init()
347 tx_ring[i].buf = 0; in dc21x4x_init()
350 tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); in dc21x4x_init()
352 tx_ring[i].next = 0; in dc21x4x_init()
361 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); in dc21x4x_init()
365 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); in dc21x4x_init()
387 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { in dc21x4x_send()
394 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); in dc21x4x_send()
[all …]
Dmt7628-eth.c136 struct fe_tx_dma *tx_ring; member
397 ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true, in mt7628_eth_send()
406 priv->tx_ring[idx].txd1 = CPHYSADDR(packet); in mt7628_eth_send()
407 priv->tx_ring[idx].txd2 &= ~TX_DMA_PLEN0; in mt7628_eth_send()
408 priv->tx_ring[idx].txd2 |= FIELD_PREP(TX_DMA_PLEN0, length); in mt7628_eth_send()
409 priv->tx_ring[idx].txd2 &= ~TX_DMA_DONE; in mt7628_eth_send()
489 memset((void *)&priv->tx_ring[i], 0, sizeof(priv->tx_ring[0])); in mt7628_eth_start()
490 priv->tx_ring[i].txd2 = TX_DMA_LS0 | TX_DMA_DONE; in mt7628_eth_start()
491 priv->tx_ring[i].txd4 = FIELD_PREP(TX_DMA_PN, 1); in mt7628_eth_start()
507 writel(CPHYSADDR((u32)&priv->tx_ring[0]), base + TX_BASE_PTR0); in mt7628_eth_start()
[all …]
Dpcnet.c70 u32 tx_ring; member
76 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; member
379 uc->tx_ring[i].base = 0; in pcnet_init()
380 uc->tx_ring[i].status = 0; in pcnet_init()
397 addr = pcnet_virt_to_mem(dev, uc->tx_ring); in pcnet_init()
398 uc->init_block.tx_ring = cpu_to_le32(addr); in pcnet_init()
402 uc->init_block.rx_ring, uc->init_block.tx_ring); in pcnet_init()
439 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; in pcnet_send()
Dmacb.c108 struct macb_dma_desc *tx_ring; member
326 macb->tx_ring[tx_head].ctrl = ctrl; in _macb_send()
327 macb->tx_ring[tx_head].addr = paddr; in _macb_send()
341 ctrl = macb->tx_ring[tx_head].ctrl; in _macb_send()
797 macb->tx_ring[i].addr = 0; in _macb_init()
799 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) | in _macb_init()
802 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); in _macb_init()
1013 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, in _macb_eth_initialize()