| /external/u-boot/board/work-microwave/work_92105/ |
| D | work_92105_spl.c | 29 .txsr = 12500000,
49 .txsr = 8333333,
|
| /external/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| D | h6_lpddr3.c | 43 u16 txsr = ns_to_t(220); in mctl_set_timing_params() local
101 writel(txsr, &mctl_ctl->dramtmg[14]); in mctl_set_timing_params()
|
| D | h6_ddr3_1333.c | 64 u16 txsr = 4; /* ? */ in mctl_set_timing_params() local
113 writel(txsr, &mctl_ctl->dramtmg[14]); in mctl_set_timing_params()
|
| /external/u-boot/board/timll/devkit3250/ |
| D | devkit3250_spl.c | 36 .txsr = 12500000,
|
| /external/u-boot/drivers/ram/ |
| D | stm32_sdram.c | 121 u8 txsr; member
201 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
211 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
|
| /external/u-boot/board/phytec/pcm052/ |
| D | pcm052.c | 125 .txsr = 506, in dram_init()
180 .txsr = 512, in dram_init()
|
| /external/u-boot/arch/arm/include/asm/arch-omap3/ |
| D | mem.h | 82 #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ argument
86 ACTIM_CTRLB_TXSR(txsr)
|
| /external/u-boot/arch/arm/include/asm/arch-vf610/ |
| D | ddrmc-vf610.h | 47 u16 txsr; member
|
| /external/u-boot/arch/arm/include/asm/arch-tegra20/ |
| D | emc.h | 49 u32 txsr; /* 0x90: EMC_TXSR */ member
|
| /external/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| D | dram.c | 47 writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); in ddr_init()
|
| /external/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| D | emc.h | 90 u32 txsr; member
|
| /external/u-boot/doc/device-tree-bindings/memory-controllers/ |
| D | st,stm32-fmc.txt | 20 txsr
|
| /external/u-boot/drivers/net/ |
| D | zynq_gem.c | 134 u32 txsr; /* 0x14 - TX Status reg */ member
361 writel(0, ®s->txsr); in zynq_gem_init()
530 return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, in zynq_gem_send()
|
| /external/u-boot/arch/arm/mach-imx/mx6/ |
| D | ddr.c | 1000 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1025 txsr = DIV_ROUND_UP(140000, clkper) - 1; in mx6_lpddr2_cfg()
1029 txsr = DIV_ROUND_UP(220000, clkper) - 1; in mx6_lpddr2_cfg()
1084 debug("txsr=%d\n", txsr); in mx6_lpddr2_cfg()
1140 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) | in mx6_lpddr2_cfg()
|
| /external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
| D | dram_spec_timing.c | 327 pdram_timing->txsr = DDR3_TDLLK; in ddr3_get_parameter()
555 pdram_timing->txsr = tmp; in lpddr2_get_parameter()
815 pdram_timing->txsr = max(2, tmp); in lpddr3_get_parameter()
1206 pdram_timing->txsr = max(2, tmp); in lpddr4_get_parameter()
|
| D | dfs.c | 508 (pdram_timing->txsr - in gen_rk3399_ctl_params_f0()
517 pdram_timing->txsr << 16); in gen_rk3399_ctl_params_f0()
525 pdram_timing->txsr << 16); in gen_rk3399_ctl_params_f0()
758 (pdram_timing->txsr - in gen_rk3399_ctl_params_f1()
768 pdram_timing->txsr << 16); in gen_rk3399_ctl_params_f1()
777 pdram_timing->txsr << 16); in gen_rk3399_ctl_params_f1()
|
| D | dram_spec_timing.h | 96 uint32_t txsr; member
|
| /external/u-boot/arch/arm/mach-imx/ |
| D | ddrmc-vf610.c | 158 DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]); in ddrmc_ctrl_init_ddr3()
|
| /external/u-boot/board/toradex/colibri_vf/ |
| D | colibri_vf.c | 125 .txsr = 506, /* changed to conform to JEDEC in dram_init()
|
| /external/u-boot/board/freescale/vf610twr/ |
| D | vf610twr.c | 119 .txsr = 468, in dram_init()
|