/external/clang/test/CodeGen/ |
D | systemz-abi-vector.c | 10 typedef __attribute__((vector_size(1))) char v1i8; typedef 42 v1i8 pass_v1i8(v1i8 arg) { return arg; } in pass_v1i8() 133 struct agg_v1i8 { v1i8 a; }; 189 v1i8 va_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, v1i8); } in va_v1i8()
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/external/llvm/include/llvm/CodeGen/ |
D | MachineValueType.h | 68 v1i8 = 21, // 1 x i8 enumerator 325 case v1i8: in getVectorElementType() 419 case v1i8: in getVectorNumElements() 452 case v1i8: in getSizeInBits() 603 if (NumElements == 1) return MVT::v1i8; in getVectorVT()
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D | ValueTypes.td | 45 def v1i8 : ValueType<16, 21>; // 1 x i8 vector value
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
D | MachineValueType.h | 71 v1i8 = 24, // 1 x i8 enumerator 436 case v1i8: in getVectorElementType() 603 case v1i8: in getVectorNumElements() 651 case v1i8: in getSizeInBits() 844 if (NumElements == 1) return MVT::v1i8; in getVectorVT()
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/external/llvm/test/CodeGen/AArch64/ |
D | trunc-v1i64.ll | 6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64. 12 ; Just like v1i16 and v1i8, there is no XTN generated.
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D | arm64-neon-copy.ll | 842 define <8 x i8> @testDUP.v1i8(<1 x i8> %a) { 843 ; CHECK-LABEL: testDUP.v1i8:
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | trunc-v1i64.ll | 6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64. 12 ; Just like v1i16 and v1i8, there is no XTN generated.
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D | arm64-neon-copy.ll | 842 define <8 x i8> @testDUP.v1i8(<1 x i8> %a) { 843 ; CHECK-LABEL: testDUP.v1i8:
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/external/llvm/lib/IR/ |
D | ValueTypes.cpp | 153 case MVT::v1i8: return "v1i8"; in getEVTString() 231 case MVT::v1i8: return VectorType::get(Type::getInt8Ty(Context), 1); in getTypeForEVT()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | ValueTypes.cpp | 150 case MVT::v1i8: return "v1i8"; in getEVTString() 231 case MVT::v1i8: return VectorType::get(Type::getInt8Ty(Context), 1); in getTypeForEVT()
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/external/llvm/test/CodeGen/ARM/ |
D | cttz_vector.ll | 5 declare <1 x i8> @llvm.cttz.v1i8(<1 x i8>, i1) 28 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 false) 212 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 true)
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | cttz_vector.ll | 5 declare <1 x i8> @llvm.cttz.v1i8(<1 x i8>, i1) 28 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 false) 212 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 true)
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64SchedFalkorDetails.td | 682 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i… 684 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2… 686 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i… 691 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v… 695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"… 696 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
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D | AArch64SchedA57.td | 348 // D form - v1i8, v1i16, v1i32, v1i64 375 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v… 411 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2… 501 // D form - v1i8, v1i16, v1i32, v1i64
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D | AArch64SchedKryoDetails.td | 214 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>; 232 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>; 262 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>; 274 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>; 1825 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
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D | AArch64SchedThunderX2T99.td | 1307 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" # 1336 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
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D | AArch64InstrFormats.td | 6141 def v1i8 : BaseSIMDThreeScalar<U, 0b001, opc, FPR8 , asm, []>; 6394 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR8 , asm, []>; 6409 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>; 6424 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR16, asm, []>;
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/external/llvm/lib/Target/AArch64/ |
D | AArch64SchedA57.td | 344 // D form - v1i8, v1i16, v1i32, v1i64 371 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v… 407 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2… 497 // D form - v1i8, v1i16, v1i32, v1i64
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D | AArch64SchedKryoDetails.td | 214 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>; 232 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>; 262 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>; 274 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>; 1805 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
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D | AArch64InstrFormats.td | 5689 def v1i8 : BaseSIMDThreeScalar<U, 0b001, opc, FPR8 , asm, []>; 5942 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR8 , asm, []>; 5957 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>; 5972 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR16, asm, []>;
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | ValueTypes.td | 47 def v1i8 : ValueType<8, 24>; // 1 x i8 vector value
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/external/llvm/utils/TableGen/ |
D | CodeGenTarget.cpp | 81 case MVT::v1i8: return "MVT::v1i8"; in getEnumName()
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/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
D | CodeGenTarget.cpp | 89 case MVT::v1i8: return "MVT::v1i8"; in getEnumName()
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/external/llvm/include/llvm/IR/ |
D | Intrinsics.td | 178 def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
D | Intrinsics.td | 206 def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8
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