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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
D	vec-min-04.ll	`8 ; CHECK: vmng %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmng %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmng %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmng %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmnlg %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmnlg %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmnlg %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmnlg %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-min-02.ll	`8 ; CHECK: vmnh %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmnh %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmnh %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmnh %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmnlh %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmnlh %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmnlh %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmnlh %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-min-03.ll	`8 ; CHECK: vmnf %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmnf %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmnf %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmnf %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmnlf %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmnlf %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmnlf %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmnlf %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-max-01.ll	`8 ; CHECK: vmxb %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmxb %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmxb %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmxb %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmxlb %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmxlb %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmxlb %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmxlb %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-max-04.ll	`8 ; CHECK: vmxg %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmxg %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmxg %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmxg %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmxlg %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmxlg %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmxlg %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmxlg %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-min-01.ll	`8 ; CHECK: vmnb %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmnb %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmnb %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmnb %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmnlb %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmnlb %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmnlb %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmnlb %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-max-03.ll	`8 ; CHECK: vmxf %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmxf %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmxf %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmxf %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmxlf %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmxlf %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmxlf %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmxlf %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-max-02.ll	`8 ; CHECK: vmxh %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmxh %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmxh %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmxh %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmxlh %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmxlh %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmxlh %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmxlh %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-perm-01.ll	`8 ; CHECK: vrepb %v24, %v24, 0 18 ; CHECK: vrepb %v24, %v24, 15 32 ; CHECK: vrepb %v24, %v24, 4 45 ; CHECK: vreph %v24, %v24, 0 55 ; CHECK: vreph %v24, %v24, 7 67 ; CHECK: vreph %v24, %v24, 2 78 ; CHECK: vrepf %v24, %v24, 0 88 ; CHECK: vrepf %v24, %v24, 3 99 ; CHECK: vrepf %v24, %v24, 1 109 ; CHECK: vrepg %v24, %v24, 0 [all …]`
D	vec-sext.ll	`9 ; CHECK: vuphb %v24, %v24 17 ; CHECK: vuphb %v0, %v24 18 ; CHECK-NEXT: vuphh %v24, %v0 26 ; CHECK: vuphb %v0, %v24 28 ; CHECK-NEXT: vuphf %v24, %v0 36 ; CHECK: vuphh %v24, %v24 44 ; CHECK: vuphh %v0, %v24 45 ; CHECK-NEXT: vuphf %v24, %v0 53 ; CHECK: vuphf %v24, %v24 61 ; CHECK: vuphb %v24, %v24 [all …]`
D	vec-zext.ll	`9 ; CHECK: vuplhb %v24, %v24 17 ; CHECK: vuplhb %v0, %v24 18 ; CHECK-NEXT: vuplhh %v24, %v0 26 ; CHECK: vuplhb %v0, %v24 28 ; CHECK-NEXT: vuplhf %v24, %v0 36 ; CHECK: vuplhh %v24, %v24 44 ; CHECK: vuplhh %v0, %v24 45 ; CHECK-NEXT: vuplhf %v24, %v0 53 ; CHECK: vuplhf %v24, %v24 61 ; CHECK: vuplhb %v24, %v24 [all …]`
D	vec-cmp-05.ll	8 ; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 9 ; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 18 ; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]] 28 ; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 29 ; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 42 ; CHECK: vo %v24, [[RES1]], [[RES0]] 52 ; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 53 ; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 62 ; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]] 72 ; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 [all …]
D	vec-perm-08.ll	`8 ; CHECK: vpdi %v24, %v24, %v26, 1 21 ; CHECK: vpdi %v24, %v26, %v24, 4 34 ; CHECK: vpdi %v24, %v24, %v26, 4 47 ; CHECK: vpdi %v24, %v26, %v24, 1 60 ; CHECK: vpdi %v24, %v24, %v24, 4 73 ; CHECK: vpdi %v24, %v24, %v26, 1 84 ; CHECK: vpdi %v24, %v26, %v24, 4 95 ; CHECK: vpdi %v24, %v24, %v26, 1 105 ; CHECK: vpdi %v24, %v26, %v24, 4 115 ; CHECK: vpdi %v24, %v24, %v26, 1 [all …]`
D	vec-cmpsel.ll	`10 ; CHECK-NEXT: vceqb %v0, %v24, %v26 11 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0 21 ; CHECK-NEXT: vceqb %v0, %v24, %v26 23 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0 33 ; CHECK-NEXT: vceqb %v0, %v24, %v26 34 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0 44 ; CHECK-NEXT: vceqb %v0, %v24, %v26 48 ; CHECK-NEXT: vsel %v24, %v28, %v25, [[REG0]] 60 ; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v24, %v28 61 ; CHECK-DAG: vsel %v24, %v25, %v29, [[REG1]] [all …]`
/external/llvm/test/CodeGen/SystemZ/
D	vec-max-03.ll	`8 ; CHECK: vmxf %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmxf %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmxf %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmxf %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmxlf %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmxlf %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmxlf %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmxlf %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-min-03.ll	`8 ; CHECK: vmnf %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmnf %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmnf %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmnf %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmnlf %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmnlf %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmnlf %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmnlf %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-max-01.ll	`8 ; CHECK: vmxb %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmxb %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmxb %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmxb %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmxlb %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmxlb %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmxlb %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmxlb %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-min-04.ll	`8 ; CHECK: vmng %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmng %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmng %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmng %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmnlg %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmnlg %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmnlg %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmnlg %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-min-02.ll	`8 ; CHECK: vmnh %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmnh %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmnh %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmnh %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmnlh %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmnlh %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmnlh %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmnlh %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-max-04.ll	`8 ; CHECK: vmxg %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmxg %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmxg %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmxg %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmxlg %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmxlg %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmxlg %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmxlg %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-max-02.ll	`8 ; CHECK: vmxh %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmxh %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmxh %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmxh %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmxlh %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmxlh %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmxlh %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmxlh %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-min-01.ll	`8 ; CHECK: vmnb %v24, {{%v24, %v26\|%v26, %v24}} 18 ; CHECK: vmnb %v24, {{%v24, %v26\|%v26, %v24}} 28 ; CHECK: vmnb %v24, {{%v24, %v26\|%v26, %v24}} 38 ; CHECK: vmnb %v24, {{%v24, %v26\|%v26, %v24}} 48 ; CHECK: vmnlb %v24, {{%v24, %v26\|%v26, %v24}} 58 ; CHECK: vmnlb %v24, {{%v24, %v26\|%v26, %v24}} 68 ; CHECK: vmnlb %v24, {{%v24, %v26\|%v26, %v24}} 78 ; CHECK: vmnlb %v24, {{%v24, %v26\|%v26, %v24}}`
D	vec-perm-01.ll	`8 ; CHECK: vrepb %v24, %v24, 0 18 ; CHECK: vrepb %v24, %v24, 15 32 ; CHECK: vrepb %v24, %v24, 4 45 ; CHECK: vreph %v24, %v24, 0 55 ; CHECK: vreph %v24, %v24, 7 67 ; CHECK: vreph %v24, %v24, 2 78 ; CHECK: vrepf %v24, %v24, 0 88 ; CHECK: vrepf %v24, %v24, 3 99 ; CHECK: vrepf %v24, %v24, 1 109 ; CHECK: vrepg %v24, %v24, 0 [all …]`
D	vec-cmp-05.ll	8 ; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 9 ; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 18 ; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]] 28 ; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 29 ; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 42 ; CHECK: vo %v24, [[RES1]], [[RES0]] 52 ; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 53 ; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 62 ; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]] 72 ; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 [all …]
D	vec-perm-08.ll	`8 ; CHECK: vpdi %v24, %v24, %v26, 1 21 ; CHECK: vpdi %v24, %v26, %v24, 4 34 ; CHECK: vpdi %v24, %v24, %v26, 4 47 ; CHECK: vpdi %v24, %v26, %v24, 1 60 ; CHECK: vpdi %v24, %v24, %v24, 4 73 ; CHECK: vpdi %v24, %v24, %v26, 1 84 ; CHECK: vpdi %v24, %v26, %v24, 4 95 ; CHECK: vpdi %v24, %v24, %v26, 1 105 ; CHECK: vpdi %v24, %v26, %v24, 4 115 ; CHECK: vpdi %v24, %v24, %v26, 1 [all …]`

12 3 4 5 6 7 8 9 10 >>...29

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