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Searched refs:v8i32 (Results 1 – 25 of 131) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
154 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
155 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
156 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
197 { ISD::SHL, MVT::v8i32, 2 }, in getArithmeticInstrCost()
198 { ISD::SRL, MVT::v8i32, 4 }, in getArithmeticInstrCost()
199 { ISD::SRA, MVT::v8i32, 4 }, in getArithmeticInstrCost()
226 { ISD::SDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
230 { ISD::UDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
[all …]
DX86InstrSSE.td340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
420 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
425 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
426 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
427 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
428 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
429 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
431 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
[all …]
DX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
340 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
362 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
403 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
445 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
520 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
536 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
555 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp336 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
337 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
338 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
339 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
366 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
367 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
370 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
371 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
379 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) in getArithmeticInstrCost()
381 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td54 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
59 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
60 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
61 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
62 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
63 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
65 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
70 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
75 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
80 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
[all …]
DX86InstrSSE.td146 [(set VR256:$dst, (v8i32 immAllZerosV))]>;
157 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
161 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
305 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
308 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)))), sub_xmm)>;
600 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
608 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1129 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, i256mem, v8f32, v8i32, loadv4i64,
1441 (v8i32 (X86cvtp2Int (v8f32 VR256:$src))))]>,
1446 (v8i32 (X86cvtp2Int (loadv8f32 addr:$src))))]>,
[all …]
DX86CallingConv.td116 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
147 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
299 CCIfType<[v8f32, v4f64, v8i32, v4i64],
544 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
566 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
610 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
669 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
727 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.gather4.ll86 …%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> unde…
153 …%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> unde…
179 …%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
205 …%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
218 …%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> un…
272 …%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> unde…
298 …%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
324 …%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
337 …%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> un…
378 …%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dpr28515.ll10 …%wide.masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* bitcast (i32* getele…
14 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) #0
Dbitcast-setcc-256.ll63 define i8 @v8i32(<8 x i32> %a, <8 x i32> %b) {
64 ; SSE2-SSSE3-LABEL: v8i32:
74 ; AVX1-LABEL: v8i32:
86 ; AVX2-LABEL: v8i32:
94 ; AVX512F-LABEL: v8i32:
102 ; AVX512BW-LABEL: v8i32:
Dbitcast-and-setcc-256.ll242 define i8 @v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
243 ; SSE2-SSSE3-LABEL: v8i32:
257 ; AVX1-LABEL: v8i32:
276 ; AVX2-LABEL: v8i32:
291 ; AVX512F-LABEL: v8i32:
300 ; AVX512BW-LABEL: v8i32:
/external/llvm/test/CodeGen/X86/
Dpr28515.ll10 …%wide.masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* bitcast (i32* getele…
14 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) #0
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h90 v8i32 = 41, // 8 x i32 enumerator
259 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
345 case v8i32: in getVectorElementType()
398 case v8i32: in getVectorNumElements()
492 case v8i32: in getSizeInBits()
627 if (NumElements == 8) return MVT::v8i32; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Instrumentation/AddressSanitizer/
Dasan-masked-load-store.ll14 @v8i32 = global <8 x i32>* zeroinitializer, align 8
19 declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) argmemonly noun…
40 define void @store.v8i32.10010110(<8 x i32> %arg) sanitize_address {
41 ; ALL-LABEL: @store.v8i32.10010110
42 %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8
56 ; STORE: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x…
57 …tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> <i1…
150 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) argmemonly …
153 define <8 x i32> @load.v8i32.11100001(<8 x i32> %arg) sanitize_address {
154 ; ALL-LABEL: @load.v8i32.11100001
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/X86/
Dbswap.ll16 declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
76 …nd an estimated cost of 14 for instruction: %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
80 …und an estimated cost of 2 for instruction: %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
84 …und an estimated cost of 4 for instruction: %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
88 …und an estimated cost of 1 for instruction: %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
91 %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
202 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
447 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 }, in getCmpSelInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h93 v8i32 = 44, // 8 x i32 enumerator
363 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
468 case v8i32: in getVectorElementType()
557 case v8i32: in getVectorNumElements()
717 case v8i32: in getSizeInBits()
868 if (NumElements == 8) return MVT::v8i32; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/StructurizeCFG/
Drebuild-ssa-infinite-loop.ll24 …%tmp8 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp5, <8 x i32> unde…
52 declare <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Daarch64-addv.ll41 declare i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32>)
57 %r = call i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32> %9)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td114 …CCIfType<[i64, f64, v2i32, v2f32, v4i32, v4f32, v8i32, v8f32, v16i32, v16f32, v2i64, v2f64, v4i16,…
118 CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,
131 …CCIfType<[i64, f64, v2i32, v2f32, v4i32, v4f32, v8i32, v8f32, v16i32, v16f32, v2i64, v2f64, v4i16,…
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp115 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
116 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
126 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
146 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
147 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td2394 defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
2525 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
2536 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2542 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm,
2556 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc,
2570 (name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da,
2584 (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc),
2595 (int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc,
2659 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2665 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
[all …]
/external/llvm/test/Analysis/CostModel/X86/
Dctbits-cost.ll16 declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>)
52 %ctpop = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %a)
100 declare <8 x i32> @llvm.ctlz.v8i32(<8 x i32>, i1)
163 %ctlz = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %a, i1 0)
172 %ctlz = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %a, i1 1)
256 declare <8 x i32> @llvm.cttz.v8i32(<8 x i32>, i1)
319 %cttz = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %a, i1 0)
328 %cttz = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %a, i1 1)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp176 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
177 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
187 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
207 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
208 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp296 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
304 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
305 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
306 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
307 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
601 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 }, in getCmpSelInstrCost()

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