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Searched refs:v_div_fixup_f16 (Results 1 – 16 of 16) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dvop3-gfx9.s230 v_div_fixup_f16 v5, v1, 0.5, v3 label
233 v_div_fixup_f16 v5, v1, v2, 0.5 label
236 v_div_fixup_f16 v5, -v1, v2, v3 label
239 v_div_fixup_f16 v5, |v1|, v2, v3 label
242 v_div_fixup_f16 v5, v1, v2, v3 clamp label
245 v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] label
248 v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] label
251 v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] label
Dvop3.s461 v_div_fixup_f16 v5, 0.5, v2, v3 label
464 v_div_fixup_f16 v5, v1, 0.5, v3 label
467 v_div_fixup_f16 v5, v1, v2, 0.5 label
470 v_div_fixup_f16 v5, v1, v2, -4.0 label
473 v_div_fixup_f16 v5, -v1, v2, v3 label
476 v_div_fixup_f16 v5, v1, |v2|, v3 label
479 v_div_fixup_f16 v5, v1, v2, v3 clamp label
Dgfx8_asm_all.s52266 v_div_fixup_f16 v5, v1, v2, v3 label
52269 v_div_fixup_f16 v255, v1, v2, v3 label
52272 v_div_fixup_f16 v5, v255, v2, v3 label
52275 v_div_fixup_f16 v5, s1, v2, v3 label
52278 v_div_fixup_f16 v5, s101, v2, v3 label
52281 v_div_fixup_f16 v5, flat_scratch_lo, v2, v3 label
52284 v_div_fixup_f16 v5, flat_scratch_hi, v2, v3 label
52287 v_div_fixup_f16 v5, vcc_lo, v2, v3 label
52290 v_div_fixup_f16 v5, vcc_hi, v2, v3 label
52293 v_div_fixup_f16 v5, tba_lo, v2, v3 label
[all …]
Dgfx9_asm_all.s47083 v_div_fixup_f16 v5, v1, v2, v3 label
47086 v_div_fixup_f16 v255, v1, v2, v3 label
47089 v_div_fixup_f16 v5, v255, v2, v3 label
47092 v_div_fixup_f16 v5, s1, v2, v3 label
47095 v_div_fixup_f16 v5, s101, v2, v3 label
47098 v_div_fixup_f16 v5, flat_scratch_lo, v2, v3 label
47101 v_div_fixup_f16 v5, flat_scratch_hi, v2, v3 label
47104 v_div_fixup_f16 v5, vcc_lo, v2, v3 label
47107 v_div_fixup_f16 v5, vcc_hi, v2, v3 label
47110 v_div_fixup_f16 v5, m0, v2, v3 label
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.div.fixup.f16.ll9 ; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
30 ; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
49 ; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
68 ; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
86 ; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[AB_F16]], v[[AB_F16]], v[[C_F16]]
102 ; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[BC_F16]], v[[BC_F16]]
118 ; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[AC_F16]], v[[B_F16]], v[[AC_F16]]
Dfdiv.f16.ll33 ; GFX8_9: v_div_fixup_f16 [[RESULT:v[0-9]+]], [[CVT_BACK]], [[RHS]], [[LHS]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dvop3_gfx9.txt33 # GFX9: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
36 # GFX9: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
39 # GFX9: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
42 # GFX9: v_div_fixup_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4]
45 # GFX9: v_div_fixup_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x0…
48 # GFX9: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x07,0xd2,0x01,0x05,…
51 # GFX9: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x07,0xd2,0x01,0x05,…
54 # GFX9: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x07,0xd2,0x01,0x05,…
57 # GFX9: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x0…
Dvop3_vi.txt255 # CHECK: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
258 # CHECK: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
261 # CHECK: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
264 # CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
267 # CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x…
270 # CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x…
Dgfx8_dasm_all.txt48690 # CHECK: v_div_fixup_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
48693 # CHECK: v_div_fixup_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
48696 # CHECK: v_div_fixup_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xff,0x05,0x0e,0x04]
48699 # CHECK: v_div_fixup_f16 v5, s1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x04,0x0e,0x04]
48702 # CHECK: v_div_fixup_f16 v5, s101, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x65,0x04,0x0e,0x04]
48705 # CHECK: v_div_fixup_f16 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x66,0x04,…
48708 # CHECK: v_div_fixup_f16 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x67,0x04,…
48711 # CHECK: v_div_fixup_f16 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x6a,0x04,0x0e,0x04]
48714 # CHECK: v_div_fixup_f16 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x6b,0x04,0x0e,0x04]
48717 # CHECK: v_div_fixup_f16 v5, tba_lo, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x6c,0x04,0x0e,0x04]
[all …]
Dgfx9_dasm_all.txt44409 # CHECK: v_div_fixup_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
44412 # CHECK: v_div_fixup_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
44415 # CHECK: v_div_fixup_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0xff,0x05,0x0e,0x04]
44418 # CHECK: v_div_fixup_f16 v5, s1, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x04,0x0e,0x04]
44421 # CHECK: v_div_fixup_f16 v5, s101, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x65,0x04,0x0e,0x04]
44424 # CHECK: v_div_fixup_f16 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x66,0x04,…
44427 # CHECK: v_div_fixup_f16 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x67,0x04,…
44430 # CHECK: v_div_fixup_f16 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x6a,0x04,0x0e,0x04]
44433 # CHECK: v_div_fixup_f16 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x6b,0x04,0x0e,0x04]
44436 # CHECK: v_div_fixup_f16 v5, m0, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x7c,0x04,0x0e,0x04]
[all …]
/external/mesa3d/src/amd/compiler/
Daco_ir.cpp291 case aco_opcode::v_div_fixup_f16: in can_use_opsel()
Daco_validate.cpp683 case aco_opcode::v_div_fixup_f16: in get_subdword_bytes_written()
Daco_register_allocation.cpp452 case aco_opcode::v_div_fixup_f16: in get_subdword_definition_info()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DVOP3Instructions.td415 def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fix…
789 defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUAsmGFX8.rst1193 …v_div_fixup_f16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :re…
DAMDGPUAsmGFX9.rst1374 …v_div_fixup_f16 dst, src0, src1, src2 :ref:`vop3_op_sel<amdgpu_synid_vop3_…