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/external/llvm/test/Transforms/EarlyCSE/
Dinvariant-loads.ll7 ; CHECK: %val0 = load i32, i32* %ptr, !invariant.load !0
8 ; CHECK: call void @clobber_and_use(i32 %val0)
9 ; CHECK: call void @clobber_and_use(i32 %val0)
10 ; CHECK: call void @clobber_and_use(i32 %val0)
13 %val0 = load i32, i32* %ptr, !invariant.load !{}
14 call void @clobber_and_use(i32 %val0)
28 ; CHECK: %val0 = load i32, i32* %ptr, !invariant.load !0
29 ; CHECK: call void @clobber_and_use(i32 %val0)
30 ; CHECK: call void @clobber_and_use(i32 %val0)
32 %val0 = load i32, i32* %ptr, !invariant.load !{}
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/EarlyCSE/
Dinvariant-loads.ll8 ; CHECK: %val0 = load i32, i32* %ptr, !invariant.load !0
9 ; CHECK: call void @clobber_and_use(i32 %val0)
10 ; CHECK: call void @clobber_and_use(i32 %val0)
11 ; CHECK: call void @clobber_and_use(i32 %val0)
14 %val0 = load i32, i32* %ptr, !invariant.load !{}
15 call void @clobber_and_use(i32 %val0)
27 ; CHECK: %val0 = load i32, i32* %ptr, !invariant.load !0
28 ; CHECK: call void @clobber_and_use(i32 %val0)
29 ; CHECK: call void @clobber_and_use(i32 %val0)
31 %val0 = load i32, i32* %ptr, !invariant.load !{}
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dmulwide.ll9 %val0 = sext i16 %a to i32
11 %val2 = mul i32 %val0, %val1
20 %val0 = zext i16 %a to i32
22 %val2 = mul i32 %val0, %val1
31 %val0 = sext i8 %a to i32
33 %val2 = mul i32 %val0, %val1
42 %val0 = zext i8 %a to i32
44 %val2 = mul i32 %val0, %val1
53 %val0 = sext i32 %a to i64
55 %val2 = mul i64 %val0, %val1
[all …]
Dbfe.ll9 %val0 = ashr i32 %a, 4
10 %val1 = and i32 %val0, 15
19 %val0 = ashr i32 %a, 3
20 %val1 = and i32 %val0, 7
29 %val0 = ashr i32 %a, 5
30 %val1 = and i32 %val0, 7
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dmulwide.ll9 %val0 = sext i16 %a to i32
11 %val2 = mul i32 %val0, %val1
20 %val0 = zext i16 %a to i32
22 %val2 = mul i32 %val0, %val1
31 %val0 = sext i8 %a to i32
33 %val2 = mul i32 %val0, %val1
42 %val0 = zext i8 %a to i32
44 %val2 = mul i32 %val0, %val1
53 %val0 = sext i32 %a to i64
55 %val2 = mul i64 %val0, %val1
[all …]
Dbfe.ll9 %val0 = ashr i32 %a, 4
10 %val1 = and i32 %val0, 15
19 %val0 = ashr i32 %a, 3
20 %val1 = and i32 %val0, 7
29 %val0 = ashr i32 %a, 5
30 %val1 = and i32 %val0, 7
/external/libaom/libaom/aom_dsp/mips/
Dintrapred_msa.c158 uint32_t val0, val1; in intra_predict_dc_4x4_msa() local
164 val0 = LW(src_top); in intra_predict_dc_4x4_msa()
166 INSERT_W2_SB(val0, val1, src); in intra_predict_dc_4x4_msa()
172 val0 = __msa_copy_u_w((v4i32)store, 0); in intra_predict_dc_4x4_msa()
174 SW4(val0, val0, val0, val0, dst, dst_stride); in intra_predict_dc_4x4_msa()
179 uint32_t val0; in intra_predict_dc_tl_4x4_msa() local
184 val0 = LW(src); in intra_predict_dc_tl_4x4_msa()
185 data = (v16i8)__msa_insert_w((v4i32)data, 0, val0); in intra_predict_dc_tl_4x4_msa()
190 val0 = __msa_copy_u_w((v4i32)store, 0); in intra_predict_dc_tl_4x4_msa()
192 SW4(val0, val0, val0, val0, dst, dst_stride); in intra_predict_dc_tl_4x4_msa()
[all …]
/external/u-boot/arch/mips/mach-mscc/
Dgpio.c12 u32 val0, val1; in mscc_gpio_set_alternate() local
14 val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0)); in mscc_gpio_set_alternate()
18 val0 |= mask; in mscc_gpio_set_alternate()
21 val0 &= ~mask; in mscc_gpio_set_alternate()
24 val0 |= mask; in mscc_gpio_set_alternate()
27 val0 &= ~mask; in mscc_gpio_set_alternate()
31 writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0)); in mscc_gpio_set_alternate()
/external/igt-gpu-tools/tests/i915/
Dgem_caching.c144 uint8_t val0 = i; variable
155 igt_assert_f(cpu_ptr[j] == val0,
157 j, cpu_ptr[j], val0);
171 uint8_t val0 = i, val1; variable
174 blt_bo_fill(staging_bo, scratch_bo, val0);
179 val1 = val0 + 63;
190 igt_assert_f(gtt_ptr[j] == val0,
192 j, start, len, gtt_ptr[j], val0);
200 igt_assert_f(gtt_ptr[j] == val0,
202 j, start, len, gtt_ptr[j], val0);
[all …]
/external/deqp/data/gles31/shaders/es32/
Dlinkage_tessellation_uniform_types.test26 uniform float val0 = -1.25;
44 tc_out[gl_InvocationID] = val0;
77 uniform vec2 val0 = [ vec2(-1.25, 1.25) ];
95 tc_out[gl_InvocationID] = val0;
128 uniform vec3 val0 = [ vec3(-1.25, 1.25, -9.5) ];
146 tc_out[gl_InvocationID] = val0;
179 uniform vec4 val0 = [ vec4(-1.25, 1.25, -9.5, -12.2) ];
197 tc_out[gl_InvocationID] = val0;
230 uniform mat2 val0 = [ mat2(-1.25, 1.25, -9.5, -12.2) ];
248 tc_out[gl_InvocationID] = val0;
[all …]
/external/deqp/data/gles31/shaders/es31/
Dlinkage_tessellation_uniform_types.test9 uniform float val0 = -1.25;
27 tc_out[gl_InvocationID] = val0;
61 uniform vec2 val0 = [ vec2(-1.25, 1.25) ];
79 tc_out[gl_InvocationID] = val0;
113 uniform vec3 val0 = [ vec3(-1.25, 1.25, -9.5) ];
131 tc_out[gl_InvocationID] = val0;
165 uniform vec4 val0 = [ vec4(-1.25, 1.25, -9.5, -12.2) ];
183 tc_out[gl_InvocationID] = val0;
217 uniform mat2 val0 = [ mat2(-1.25, 1.25, -9.5, -12.2) ];
235 tc_out[gl_InvocationID] = val0;
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Dintrapred_msa.c156 uint32_t val0, val1; in intra_predict_dc_4x4_msa() local
162 val0 = LW(src_top); in intra_predict_dc_4x4_msa()
164 INSERT_W2_SB(val0, val1, src); in intra_predict_dc_4x4_msa()
170 val0 = __msa_copy_u_w((v4i32)store, 0); in intra_predict_dc_4x4_msa()
172 SW4(val0, val0, val0, val0, dst, dst_stride); in intra_predict_dc_4x4_msa()
177 uint32_t val0; in intra_predict_dc_tl_4x4_msa() local
182 val0 = LW(src); in intra_predict_dc_tl_4x4_msa()
183 data = (v16i8)__msa_insert_w((v4i32)data, 0, val0); in intra_predict_dc_tl_4x4_msa()
188 val0 = __msa_copy_u_w((v4i32)store, 0); in intra_predict_dc_tl_4x4_msa()
190 SW4(val0, val0, val0, val0, dst, dst_stride); in intra_predict_dc_tl_4x4_msa()
[all …]
/external/tensorflow/tensorflow/lite/toco/graph_transformations/
Dresolve_constant_binary.cc133 const auto val0 = input0_data[Offset(input0_shape, input0_indices)]; in EvaluateBinaryOperatorOnConstantInputs() local
138 outval = val0 + val1; in EvaluateBinaryOperatorOnConstantInputs()
140 outval = val0 * val1; in EvaluateBinaryOperatorOnConstantInputs()
142 outval = val0 - val1; in EvaluateBinaryOperatorOnConstantInputs()
144 outval = val0 / val1; in EvaluateBinaryOperatorOnConstantInputs()
146 outval = std::floor(val0 / val1); in EvaluateBinaryOperatorOnConstantInputs()
148 outval = val0 - (std::floor(val0 / val1) * val1); in EvaluateBinaryOperatorOnConstantInputs()
150 outval = std::min(val0, val1); in EvaluateBinaryOperatorOnConstantInputs()
152 outval = std::max(val0, val1); in EvaluateBinaryOperatorOnConstantInputs()
154 outval = val0 < val1; in EvaluateBinaryOperatorOnConstantInputs()
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dds_read2_superreg.ll18 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0, align 4
20 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
32 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0
34 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
49 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4
50 %elt0 = extractelement <4 x float> %val0, i32 0
51 %elt1 = extractelement <4 x float> %val0, i32 1
52 %elt2 = extractelement <4 x float> %val0, i32 2
53 %elt3 = extractelement <4 x float> %val0, i32 3
74 %val0 = load <3 x float>, <3 x float> addrspace(3)* %arrayidx0, align 4
[all …]
Dcgp-bitfield-extract.ll15 ; OPT-NEXT: %val0 = and i32 %0, 255
45 %val0 = and i32 %shr, 255
55 %phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]
66 ; OPT-NEXT: %val0 = and i32 %0, 255
85 %val0 = and i32 %shr, 255
95 %phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]
107 ; OPT-NEXT: %val0 = and i16 %0, 255
137 %val0 = and i16 %shr, 255
147 %phi = phi i16 [ %val0, %bb0 ], [ %val1, %bb1 ]
162 ; OPT-NEXT: %val0 = and i64 %0, 255
[all …]
Dds_read2st64.ll16 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
20 %sum = fadd float %val0, %val1
36 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
40 %sum = fadd float %val0, %val1
56 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
60 %sum = fadd float %val0, %val1
76 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
80 %sum = fadd float %val0, %val1
92 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
96 %sum = fadd float %val0, %val1
[all …]
Dannotate-kernel-features.ll31 %val0 = call i32 @llvm.r600.read.tgid.y()
32 store volatile i32 %val0, i32 addrspace(1)* %ptr
40 %val0 = call i32 @llvm.r600.read.tgid.x()
42 store volatile i32 %val0, i32 addrspace(1)* %ptr
56 %val0 = call i32 @llvm.r600.read.tgid.x()
58 store volatile i32 %val0, i32 addrspace(1)* %ptr
65 %val0 = call i32 @llvm.r600.read.tgid.y()
67 store volatile i32 %val0, i32 addrspace(1)* %ptr
74 %val0 = call i32 @llvm.r600.read.tgid.x()
77 store volatile i32 %val0, i32 addrspace(1)* %ptr
[all …]
Dds_read2.ll18 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
22 %sum = fadd float %val0, %val1
37 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
41 %sum = fadd float %val0, %val1
55 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
59 %sum = fadd float %val0, %val1
73 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
78 %sum.0 = fadd float %val0, %val1
105 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
110 %sum.0 = fadd float %val0, %val1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dds_read2_superreg.ll18 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0, align 4
20 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
32 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0
34 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
49 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4
50 %elt0 = extractelement <4 x float> %val0, i32 0
51 %elt1 = extractelement <4 x float> %val0, i32 1
52 %elt2 = extractelement <4 x float> %val0, i32 2
53 %elt3 = extractelement <4 x float> %val0, i32 3
74 %val0 = load <3 x float>, <3 x float> addrspace(3)* %arrayidx0, align 4
[all …]
Dcgp-bitfield-extract.ll15 ; OPT-NEXT: %val0 = and i32 %0, 255
45 %val0 = and i32 %shr, 255
55 %phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]
66 ; OPT-NEXT: %val0 = and i32 %0, 255
85 %val0 = and i32 %shr, 255
95 %phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]
107 ; OPT-NEXT: %val0 = and i16 %0, 255
143 %val0 = and i16 %shr, 255
153 %phi = phi i16 [ %val0, %bb0 ], [ %val1, %bb1 ]
168 ; OPT-NEXT: %val0 = and i64 %0, 255
[all …]
Dannotate-kernel-features.ll31 %val0 = call i32 @llvm.r600.read.tgid.y()
32 store volatile i32 %val0, i32 addrspace(1)* %ptr
40 %val0 = call i32 @llvm.r600.read.tgid.x()
42 store volatile i32 %val0, i32 addrspace(1)* %ptr
56 %val0 = call i32 @llvm.r600.read.tgid.x()
58 store volatile i32 %val0, i32 addrspace(1)* %ptr
65 %val0 = call i32 @llvm.r600.read.tgid.y()
67 store volatile i32 %val0, i32 addrspace(1)* %ptr
74 %val0 = call i32 @llvm.r600.read.tgid.x()
77 store volatile i32 %val0, i32 addrspace(1)* %ptr
[all …]
Dds_read2st64.ll20 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
24 %sum = fadd float %val0, %val1
43 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
47 %sum = fadd float %val0, %val1
66 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
70 %sum = fadd float %val0, %val1
89 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
93 %sum = fadd float %val0, %val1
108 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
112 %sum = fadd float %val0, %val1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dlogical-imm.ll9 %val0 = and i32 %in32, 2863311530
10 store volatile i32 %val0, i32* @var32
31 %val0 = or i32 %in32, 2863311530
32 store volatile i32 %val0, i32* @var32
53 %val0 = xor i32 %in32, 2863311530
54 store volatile i32 %val0, i32* @var32
74 %val0 = add i32 %in32, 2863311530
75 store i32 %val0, i32* @var32
/external/llvm/test/CodeGen/AArch64/
Dlogical-imm.ll9 %val0 = and i32 %in32, 2863311530
10 store volatile i32 %val0, i32* @var32
31 %val0 = or i32 %in32, 2863311530
32 store volatile i32 %val0, i32* @var32
53 %val0 = xor i32 %in32, 2863311530
54 store volatile i32 %val0, i32* @var32
74 %val0 = add i32 %in32, 2863311530
75 store i32 %val0, i32* @var32
/external/u-boot/board/mscc/jr2/
Djr2.c39 u32 val0, val1; in vcoreiii_gpio_set_alternate() local
52 val0 = readl(reg0); in vcoreiii_gpio_set_alternate()
55 writel(val0 | mask, reg0); in vcoreiii_gpio_set_alternate()
58 writel(val0 & ~mask, reg0); in vcoreiii_gpio_set_alternate()
61 writel(val0 | mask, reg0); in vcoreiii_gpio_set_alternate()
64 writel(val0 & ~mask, reg0); in vcoreiii_gpio_set_alternate()

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