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Searched refs:val2 (Results 1 – 25 of 623) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/SystemZ/
Dcmp-ext.ll4 define i8 @fun0(i8 %val1, i8 %val2) {
5 %cmp = icmp eq i8 %val1, %val2
10 ; CHECK: cost of 3 for instruction: %cmp = icmp eq i8 %val1, %val2
14 define i16 @fun1(i8 %val1, i8 %val2) {
15 %cmp = icmp eq i8 %val1, %val2
20 ; CHECK: cost of 3 for instruction: %cmp = icmp eq i8 %val1, %val2
24 define i32 @fun2(i8 %val1, i8 %val2) {
25 %cmp = icmp eq i8 %val1, %val2
30 ; CHECK: cost of 3 for instruction: %cmp = icmp eq i8 %val1, %val2
34 define i64 @fun3(i8 %val1, i8 %val2) {
[all …]
Dcmpsel.ll8 define i8 @fun0(i8 %val1, i8 %val2,
10 %cmp = icmp eq i8 %val1, %val2
15 ; CHECK: cost of 3 for instruction: %cmp = icmp eq i8 %val1, %val2
19 define i16 @fun1(i8 %val1, i8 %val2,
21 %cmp = icmp eq i8 %val1, %val2
26 ; CHECK: cost of 3 for instruction: %cmp = icmp eq i8 %val1, %val2
30 define i32 @fun2(i8 %val1, i8 %val2,
32 %cmp = icmp eq i8 %val1, %val2
37 ; CHECK: cost of 3 for instruction: %cmp = icmp eq i8 %val1, %val2
41 define i64 @fun3(i8 %val1, i8 %val2,
[all …]
Dscalar-cmp-cmp-log-sel.ll5 define i8 @fun0(i8 %val1, i8 %val2, i8 %val3, i8 %val4,
7 %cmp0 = icmp eq i8 %val1, %val2
14 ; CHECK: cost of 3 for instruction: %cmp0 = icmp eq i8 %val1, %val2
20 define i16 @fun1(i8 %val1, i8 %val2, i8 %val3, i8 %val4,
22 %cmp0 = icmp eq i8 %val1, %val2
29 ; CHECK: cost of 3 for instruction: %cmp0 = icmp eq i8 %val1, %val2
35 define i32 @fun2(i8 %val1, i8 %val2, i8 %val3, i8 %val4,
37 %cmp0 = icmp eq i8 %val1, %val2
44 ; CHECK: cost of 3 for instruction: %cmp0 = icmp eq i8 %val1, %val2
50 define i64 @fun3(i8 %val1, i8 %val2, i8 %val3, i8 %val4,
[all …]
/external/libcxx/test/libcxx/atomics/
Ddiagnose_invalid_memory_order.fail.cpp27 int val2 = 2; ((void)val2); in main() local
78 …x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_release); // expe… in main()
79 …x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acq_rel); // expe… in main()
80 …vx.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_release); // exp… in main()
81 …vx.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acq_rel); // exp… in main()
83 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_relaxed); in main()
84 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_consume); in main()
85 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acquire); in main()
86 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_seq_cst); in main()
89 x.compare_exchange_weak(val1, val2, std::memory_order_release); in main()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-move-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 ret <16 x i8> %val2
14 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
18 ret <8 x i16> %val2
22 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
26 ret <4 x i32> %val2
30 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
34 ret <2 x i64> %val2
38 define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
42 ret <4 x float> %val2
[all …]
Dvec-min-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val2, %val1
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val2, %val1
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val2, %val1
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-min-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val2, %val1
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val2, %val1
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val2, %val1
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-min-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val2, %val1
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val2, %val1
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val2, %val1
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-max-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val1, %val2
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val1, %val2
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val1, %val2
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-max-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val1, %val2
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val1, %val2
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val1, %val2
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-min-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val2, %val1
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val2, %val1
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val2, %val1
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-max-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val1, %val2
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val1, %val2
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val1, %val2
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-max-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val1, %val2
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val1, %val2
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val1, %val2
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 ret <16 x i8> %val2
14 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
18 ret <8 x i16> %val2
22 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
26 ret <4 x i32> %val2
30 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
34 ret <2 x i64> %val2
38 define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
42 ret <4 x float> %val2
[all …]
Dvec-max-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val1, %val2
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val1, %val2
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val1, %val2
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-min-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val2, %val1
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val2, %val1
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val2, %val1
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-max-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val1, %val2
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val1, %val2
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val1, %val2
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-min-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val2, %val1
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val2, %val1
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val2, %val1
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-min-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val2, %val1
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val2, %val1
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val2, %val1
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-max-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val1, %val2
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val1, %val2
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val1, %val2
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-max-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val1, %val2
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val1, %val2
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val1, %val2
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-min-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val2, %val1
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val2, %val1
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val2, %val1
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
/external/libbrillo/brillo/
Dany_unittest.cc19 Any val2 = val; in TEST() local
21 EXPECT_TRUE(val2.IsEmpty()); in TEST()
34 Any val2(3.1415926); in TEST() local
35 EXPECT_FALSE(val2.IsEmpty()); in TEST()
36 EXPECT_TRUE(val2.IsTypeCompatible<double>()); in TEST()
37 EXPECT_FALSE(val2.IsTypeCompatible<int>()); in TEST()
38 EXPECT_DOUBLE_EQ(3.1415926, val2.Get<double>()); in TEST()
66 Any val2; in TEST() local
67 EXPECT_TRUE(val2.IsEmpty()); in TEST()
68 val2 = val; in TEST()
[all …]
/external/jemalloc_new/test/unit/
Datomic.c18 #define DO_TESTS(t, ta, val1, val2, val3) do { \ argument
31 atomic_store_##ta(&atom, val2, ATOMIC_RELAXED); \
33 assert_##ta##_eq(val2, val, "Store failed"); \
37 val = atomic_exchange_##ta(&atom, val2, ATOMIC_RELAXED); \
40 assert_##ta##_eq(val2, val, "Exchange store invalid value"); \
49 expected = val2; \
55 assert_b_eq(val1 == val2, success, \
68 expected = val2; \
71 assert_b_eq(val1 == val2, success, \
85 #define DO_INTEGER_TESTS(t, ta, val1, val2) do { \ argument
[all …]
/external/pdfium/core/fxcodec/jbig2/
DJBig2_BitStream_unittest.cpp21 int32_t val2; in TEST() local
22 EXPECT_EQ(0, stream.readNBits(1, &val2)); in TEST()
23 EXPECT_EQ(0, val2); in TEST()
25 EXPECT_EQ(0, stream.readNBits(2, &val2)); in TEST()
26 EXPECT_EQ(3, val2); in TEST()
28 EXPECT_EQ(0, stream.readNBits(4, &val2)); in TEST()
29 EXPECT_EQ(1, val2); in TEST()
47 int32_t val2; in TEST() local
48 EXPECT_EQ(-1, stream.readNBits(2, &val2)); in TEST()
58 int32_t val2; in TEST() local
[all …]

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