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Searched refs:vavgub (Results 1 – 25 of 30) sorted by relevance

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/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs93 0x10,0x43,0x24,0x02 = vavgub 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dv6-inlasm1.ll86 %v55 = call <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32> %v53, <16 x i32> %v54)
108 declare <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32>, <16 x i32>) #1
Dintrinsics-v60-alu.ll319 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32> %a, <16 x i32> %b)
953 declare <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32>, <16 x i32>) #0
Dv60Intrins.ll1001 %497 = call <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32> %495, <16 x i32> %496)
2057 declare <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32>, <16 x i32>) #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt282 # CHECK: r17:16 = vavgub(r21:20,r31:30)
284 # CHECK: r17:16 = vavgub(r21:20,r31:30):rnd
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt282 # CHECK: r17:16 = vavgub(r21:20, r31:30)
284 # CHECK: r17:16 = vavgub(r21:20, r31:30):rnd
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s398 # CHECK-BE: vavgub 2, 3, 4 # encoding: [0x10,0x43,0x24,0x02]
399 # CHECK-LE: vavgub 2, 3, 4 # encoding: [0x02,0x24,0x43,0x10]
400 vavgub 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s398 # CHECK-BE: vavgub 2, 3, 4 # encoding: [0x10,0x43,0x24,0x02]
399 # CHECK-LE: vavgub 2, 3, 4 # encoding: [0x02,0x24,0x43,0x10]
400 vavgub 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll753 declare i64 @llvm.hexagon.A2.vavgub(i64, i64)
755 %z = call i64 @llvm.hexagon.A2.vavgub(i64 %a, i64 %b)
758 ; CHECK: vavgub({{.*}},{{.*}})
765 ; CHECK: = vavgub({{.*}},{{.*}}):rnd
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll753 declare i64 @llvm.hexagon.A2.vavgub(i64, i64)
755 %z = call i64 @llvm.hexagon.A2.vavgub(i64 %a, i64 %b)
758 ; CHECK: vavgub({{.*}}, {{.*}})
765 ; CHECK: = vavgub({{.*}}, {{.*}}):rnd
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt363 # CHECK: vavgub 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt363 # CHECK: vavgub 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td333 def int_ppc_altivec_vavgub : PowerPC_Vec_BBB_Intrinsic<"vavgub">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td407 def int_ppc_altivec_vavgub : PowerPC_Vec_BBB_Intrinsic<"vavgub">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepMappings.td272 def V6_vavgub_altAlias : InstAlias<"$Vd32 = vavgub($Vu32,$Vv32)", (V6_vavgub HvxVR:$Vd32, HvxVR:$Vu…
273 def V6_vavgubrnd_altAlias : InstAlias<"$Vd32 = vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd HvxVR:$Vd32,…
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2363 V(vavgub, VAVGUB, 0x10000402) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td563 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td564 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1346 hexagon_A2_vavgub, // llvm.hexagon.A2.vavgub
2349 hexagon_V6_vavgub, // llvm.hexagon.V6.vavgub
2350 hexagon_V6_vavgub_128B, // llvm.hexagon.V6.vavgub.128B
4783 ppc_altivec_vavgub, // llvm.ppc.altivec.vavgub
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc3298 __ vavgub(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td895 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
903 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
/external/llvm/test/CodeGen/Hexagon/
Dv60Intrins.ll1002 %497 = call <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32> %495, <16 x i32> %496)
2058 declare <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32>, <16 x i32>) #1
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen800 hexagon_A2_vavgub, // llvm.hexagon.A2.vavgub
1697 hexagon_V6_vavgub, // llvm.hexagon.V6.vavgub
1698 hexagon_V6_vavgub_128B, // llvm.hexagon.V6.vavgub.128B
3839 ppc_altivec_vavgub, // llvm.ppc.altivec.vavgub
6824 "llvm.hexagon.A2.vavgub",
7721 "llvm.hexagon.V6.vavgub",
7722 "llvm.hexagon.V6.vavgub.128B",
9863 "llvm.ppc.altivec.vavgub",
14709 1, // llvm.hexagon.A2.vavgub
15606 1, // llvm.hexagon.V6.vavgub
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen806 hexagon_A2_vavgub, // llvm.hexagon.A2.vavgub
1703 hexagon_V6_vavgub, // llvm.hexagon.V6.vavgub
1704 hexagon_V6_vavgub_128B, // llvm.hexagon.V6.vavgub.128B
3845 ppc_altivec_vavgub, // llvm.ppc.altivec.vavgub
6864 "llvm.hexagon.A2.vavgub",
7761 "llvm.hexagon.V6.vavgub",
7762 "llvm.hexagon.V6.vavgub.128B",
9903 "llvm.ppc.altivec.vavgub",
14804 1, // llvm.hexagon.A2.vavgub
15701 1, // llvm.hexagon.V6.vavgub
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen806 hexagon_A2_vavgub, // llvm.hexagon.A2.vavgub
1703 hexagon_V6_vavgub, // llvm.hexagon.V6.vavgub
1704 hexagon_V6_vavgub_128B, // llvm.hexagon.V6.vavgub.128B
3845 ppc_altivec_vavgub, // llvm.ppc.altivec.vavgub
6864 "llvm.hexagon.A2.vavgub",
7761 "llvm.hexagon.V6.vavgub",
7762 "llvm.hexagon.V6.vavgub.128B",
9903 "llvm.ppc.altivec.vavgub",
14804 1, // llvm.hexagon.A2.vavgub
15701 1, // llvm.hexagon.V6.vavgub
[all …]

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