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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dv6-unaligned-spill.ll32 %v5 = tail call <32 x i32> @llvm.hexagon.V6.vavguh.128B(<32 x i32> %v3, <32 x i32> %v2) #2
49 declare <32 x i32> @llvm.hexagon.V6.vavguh.128B(<32 x i32>, <32 x i32>) #1
Dintrinsics-v60-alu.ll327 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavguh(<16 x i32> %a, <16 x i32> %b)
954 declare <16 x i32> @llvm.hexagon.V6.vavguh(<16 x i32>, <16 x i32>) #0
Dv60Intrins.ll1049 %533 = call <16 x i32> @llvm.hexagon.V6.vavguh(<16 x i32> %531, <16 x i32> %532)
2093 declare <16 x i32> @llvm.hexagon.V6.vavguh(<16 x i32>, <16 x i32>) #1
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs94 0x10,0x43,0x24,0x42 = vavguh 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt270 # CHECK: r17:16 = vavguh(r21:20,r31:30)
272 # CHECK: r17:16 = vavguh(r21:20,r31:30):rnd
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt270 # CHECK: r17:16 = vavguh(r21:20, r31:30)
272 # CHECK: r17:16 = vavguh(r21:20, r31:30):rnd
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s401 # CHECK-BE: vavguh 2, 3, 4 # encoding: [0x10,0x43,0x24,0x42]
402 # CHECK-LE: vavguh 2, 3, 4 # encoding: [0x42,0x24,0x43,0x10]
403 vavguh 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s401 # CHECK-BE: vavguh 2, 3, 4 # encoding: [0x10,0x43,0x24,0x42]
402 # CHECK-LE: vavguh 2, 3, 4 # encoding: [0x42,0x24,0x43,0x10]
403 vavguh 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll717 declare i64 @llvm.hexagon.A2.vavguh(i64, i64)
719 %z = call i64 @llvm.hexagon.A2.vavguh(i64 %a, i64 %b)
722 ; CHECK: = vavguh({{.*}},{{.*}})
729 ; CHECK: = vavguh({{.*}},{{.*}}):rnd
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll717 declare i64 @llvm.hexagon.A2.vavguh(i64, i64)
719 %z = call i64 @llvm.hexagon.A2.vavguh(i64 %a, i64 %b)
722 ; CHECK: = vavguh({{.*}}, {{.*}})
729 ; CHECK: = vavguh({{.*}}, {{.*}}):rnd
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt366 # CHECK: vavguh 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt366 # CHECK: vavguh 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td334 def int_ppc_altivec_vavguh : PowerPC_Vec_HHH_Intrinsic<"vavguh">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td408 def int_ppc_altivec_vavguh : PowerPC_Vec_HHH_Intrinsic<"vavguh">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepMappings.td274 def V6_vavguh_altAlias : InstAlias<"$Vd32 = vavguh($Vu32,$Vv32)", (V6_vavguh HvxVR:$Vd32, HvxVR:$Vu…
275 def V6_vavguhrnd_altAlias : InstAlias<"$Vd32 = vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd HvxVR:$Vd32,…
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2365 V(vavguh, VAVGUH, 0x10000442) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td564 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td565 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1348 hexagon_A2_vavguh, // llvm.hexagon.A2.vavguh
2353 hexagon_V6_vavguh, // llvm.hexagon.V6.vavguh
2354 hexagon_V6_vavguh_128B, // llvm.hexagon.V6.vavguh.128B
4784 ppc_altivec_vavguh, // llvm.ppc.altivec.vavguh
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc3293 __ vavguh(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td897 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
906 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
/external/llvm/test/CodeGen/Hexagon/
Dv60Intrins.ll1050 %533 = call <16 x i32> @llvm.hexagon.V6.vavguh(<16 x i32> %531, <16 x i32> %532)
2094 declare <16 x i32> @llvm.hexagon.V6.vavguh(<16 x i32>, <16 x i32>) #1
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4329 "gub\006vavguh\006vavguw\007vbpermd\007vbpermq\005vcfsx\005vcfux\007vcip"
6444 …{ 10444 /* vavguh */, PPC::VAVGUH, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, …
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen802 hexagon_A2_vavguh, // llvm.hexagon.A2.vavguh
1701 hexagon_V6_vavguh, // llvm.hexagon.V6.vavguh
1702 hexagon_V6_vavguh_128B, // llvm.hexagon.V6.vavguh.128B
3840 ppc_altivec_vavguh, // llvm.ppc.altivec.vavguh
6826 "llvm.hexagon.A2.vavguh",
7725 "llvm.hexagon.V6.vavguh",
7726 "llvm.hexagon.V6.vavguh.128B",
9864 "llvm.ppc.altivec.vavguh",
14711 1, // llvm.hexagon.A2.vavguh
15610 1, // llvm.hexagon.V6.vavguh
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen808 hexagon_A2_vavguh, // llvm.hexagon.A2.vavguh
1707 hexagon_V6_vavguh, // llvm.hexagon.V6.vavguh
1708 hexagon_V6_vavguh_128B, // llvm.hexagon.V6.vavguh.128B
3846 ppc_altivec_vavguh, // llvm.ppc.altivec.vavguh
6866 "llvm.hexagon.A2.vavguh",
7765 "llvm.hexagon.V6.vavguh",
7766 "llvm.hexagon.V6.vavguh.128B",
9904 "llvm.ppc.altivec.vavguh",
14806 1, // llvm.hexagon.A2.vavguh
15705 1, // llvm.hexagon.V6.vavguh
[all …]

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