| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s.cs | 122 0x10,0x43,0x22,0x46 = vcmpgtuh 2, 3, 4
123 0x10,0x43,0x26,0x46 = vcmpgtuh. 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 514 # CHECK-BE: vcmpgtuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x46]
515 # CHECK-LE: vcmpgtuh 2, 3, 4 # encoding: [0x46,0x22,0x43,0x10]
516 vcmpgtuh 2, 3, 4
517 # CHECK-BE: vcmpgtuh. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x46]
518 # CHECK-LE: vcmpgtuh. 2, 3, 4 # encoding: [0x46,0x26,0x43,0x10]
519 vcmpgtuh. 2, 3, 4
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 514 # CHECK-BE: vcmpgtuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x46]
515 # CHECK-LE: vcmpgtuh 2, 3, 4 # encoding: [0x46,0x22,0x43,0x10]
516 vcmpgtuh 2, 3, 4
517 # CHECK-BE: vcmpgtuh. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x46]
518 # CHECK-LE: vcmpgtuh. 2, 3, 4 # encoding: [0x46,0x26,0x43,0x10]
519 vcmpgtuh. 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | vec_cmp.ll | 202 ; CHECK: vcmpgtuh [[RET:[0-9]+]], 2, 3
221 ; CHECK: vcmpgtuh 2, 3, 2
239 ; CHECK: vcmpgtuh 2, 2, 3
258 ; CHECK: vcmpgtuh [[RET:[0-9]+]], 3, 2
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vec_cmp.ll | 202 ; CHECK: vcmpgtuh [[RET:[0-9]+]], 2, 3
221 ; CHECK: vcmpgtuh 2, 3, 2
239 ; CHECK: vcmpgtuh 2, 2, 3
258 ; CHECK: vcmpgtuh [[RET:[0-9]+]], 3, 2
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 474 # CHECK: vcmpgtuh 2, 3, 4
477 # CHECK: vcmpgtuh. 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 474 # CHECK: vcmpgtuh 2, 3, 4
477 # CHECK: vcmpgtuh. 2, 3, 4
|
| /external/v8/src/compiler/backend/ppc/ |
| D | code-generator-ppc.cc | 2782 __ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
2789 __ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
3063 SIMD_ALL_TRUE(vcmpgtuh) in AssembleArchInstruction()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 807 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
808 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 814 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
815 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
|
| /external/v8/src/codegen/ppc/ |
| D | constants-ppc.h | 1128 V(vcmpgtuh, VCMPGTUH, 0x10000246) \
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 4333 "vcmpgtub\010vcmpgtud\010vcmpgtuh\010vcmpgtuw\007vcmpneb\007vcmpneh\007v"
6485 …{ 10664 /* vcmpgtuh */, PPC::VCMPGTUH, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVR…
6486 …{ 10664 /* vcmpgtuh */, PPC::VCMPGTUHo, Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3, 0, { MCK__DOT…
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 4818 ppc_altivec_vcmpgtuh, // llvm.ppc.altivec.vcmpgtuh
4819 ppc_altivec_vcmpgtuh_p, // llvm.ppc.altivec.vcmpgtuh.p
|
| D | IntrinsicImpl.inc | 4844 "llvm.ppc.altivec.vcmpgtuh",
4845 "llvm.ppc.altivec.vcmpgtuh.p",
13722 1, // llvm.ppc.altivec.vcmpgtuh
13723 1, // llvm.ppc.altivec.vcmpgtuh.p
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 3874 ppc_altivec_vcmpgtuh, // llvm.ppc.altivec.vcmpgtuh
3875 ppc_altivec_vcmpgtuh_p, // llvm.ppc.altivec.vcmpgtuh.p
9898 "llvm.ppc.altivec.vcmpgtuh",
9899 "llvm.ppc.altivec.vcmpgtuh.p",
17783 1, // llvm.ppc.altivec.vcmpgtuh
17784 1, // llvm.ppc.altivec.vcmpgtuh.p
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 3880 ppc_altivec_vcmpgtuh, // llvm.ppc.altivec.vcmpgtuh
3881 ppc_altivec_vcmpgtuh_p, // llvm.ppc.altivec.vcmpgtuh.p
9938 "llvm.ppc.altivec.vcmpgtuh",
9939 "llvm.ppc.altivec.vcmpgtuh.p",
17878 1, // llvm.ppc.altivec.vcmpgtuh
17879 1, // llvm.ppc.altivec.vcmpgtuh.p
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 3880 ppc_altivec_vcmpgtuh, // llvm.ppc.altivec.vcmpgtuh
3881 ppc_altivec_vcmpgtuh_p, // llvm.ppc.altivec.vcmpgtuh.p
9938 "llvm.ppc.altivec.vcmpgtuh",
9939 "llvm.ppc.altivec.vcmpgtuh.p",
17878 1, // llvm.ppc.altivec.vcmpgtuh
17879 1, // llvm.ppc.altivec.vcmpgtuh.p
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 3880 ppc_altivec_vcmpgtuh, // llvm.ppc.altivec.vcmpgtuh
3881 ppc_altivec_vcmpgtuh_p, // llvm.ppc.altivec.vcmpgtuh.p
9938 "llvm.ppc.altivec.vcmpgtuh",
9939 "llvm.ppc.altivec.vcmpgtuh.p",
17878 1, // llvm.ppc.altivec.vcmpgtuh
17879 1, // llvm.ppc.altivec.vcmpgtuh.p
|
| /external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/ |
| D | Intrinsics.gen | 3880 ppc_altivec_vcmpgtuh, // llvm.ppc.altivec.vcmpgtuh
3881 ppc_altivec_vcmpgtuh_p, // llvm.ppc.altivec.vcmpgtuh.p
9938 "llvm.ppc.altivec.vcmpgtuh",
9939 "llvm.ppc.altivec.vcmpgtuh.p",
17878 1, // llvm.ppc.altivec.vcmpgtuh
17879 1, // llvm.ppc.altivec.vcmpgtuh.p
|