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Searched refs:vco_hz (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rk3036.c51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll() local
52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
57 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
58 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
Dclk_rk322x.c48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll() local
49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
53 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
54 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
Dclk_rk3188.c91 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll() local
92 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
95 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
96 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
Dclk_rk3128.c45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll() local
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
51 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
Dclk_rv1108.c72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll() local
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
77 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
78 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
Dclk_rk3288.c150 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll() local
151 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
154 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
155 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
Dclk_rk3368.c93 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll() local
94 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
97 pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
Dclk_px30.c205 uint vco_hz, output_hz; in rkclk_set_pll() local
214 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
215 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; in rkclk_set_pll()
219 rate->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
220 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()