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Searched refs:vmaxsh (Results 1 – 20 of 20) sorted by relevance

/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs97 0x10,0x43,0x21,0x42 = vmaxsh 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dppc64-P9-vabsd.ll46 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %a, <8 x i16> %sub.i)
56 ; CHECK-PWR8: vmaxsh
328 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %sub, <8 x i16> %sub.i)
336 ; CHECK-PWR8: vmaxsh
362 declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s411 # CHECK-BE: vmaxsh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x42]
412 # CHECK-LE: vmaxsh 2, 3, 4 # encoding: [0x42,0x21,0x43,0x10]
413 vmaxsh 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s411 # CHECK-BE: vmaxsh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x42]
412 # CHECK-LE: vmaxsh 2, 3, 4 # encoding: [0x42,0x21,0x43,0x10]
413 vmaxsh 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt375 # CHECK: vmaxsh 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt375 # CHECK: vmaxsh 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td340 def int_ppc_altivec_vmaxsh : PowerPC_Vec_HHH_Intrinsic<"vmaxsh">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td414 def int_ppc_altivec_vmaxsh : PowerPC_Vec_HHH_Intrinsic<"vmaxsh">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2289 V(vmaxsh, VMAXSH, 0x10000142) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td569 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td570 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2604 __ vmaxsh(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4339 "nsertw\007vlogefp\007vmaddfp\006vmaxfp\006vmaxsb\006vmaxsd\006vmaxsh\006"
6535 …{ 11015 /* vmaxsh */, PPC::VMAXSH, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, …
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc4844 ppc_altivec_vmaxsh, // llvm.ppc.altivec.vmaxsh
DIntrinsicImpl.inc4870 "llvm.ppc.altivec.vmaxsh",
13748 1, // llvm.ppc.altivec.vmaxsh
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3900 ppc_altivec_vmaxsh, // llvm.ppc.altivec.vmaxsh
9924 "llvm.ppc.altivec.vmaxsh",
17809 1, // llvm.ppc.altivec.vmaxsh
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3906 ppc_altivec_vmaxsh, // llvm.ppc.altivec.vmaxsh
9964 "llvm.ppc.altivec.vmaxsh",
17904 1, // llvm.ppc.altivec.vmaxsh
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3906 ppc_altivec_vmaxsh, // llvm.ppc.altivec.vmaxsh
9964 "llvm.ppc.altivec.vmaxsh",
17904 1, // llvm.ppc.altivec.vmaxsh
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3906 ppc_altivec_vmaxsh, // llvm.ppc.altivec.vmaxsh
9964 "llvm.ppc.altivec.vmaxsh",
17904 1, // llvm.ppc.altivec.vmaxsh
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3906 ppc_altivec_vmaxsh, // llvm.ppc.altivec.vmaxsh
9964 "llvm.ppc.altivec.vmaxsh",
17904 1, // llvm.ppc.altivec.vmaxsh