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Searched refs:vmaxsw (Results 1 – 20 of 20) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dppc64-P9-vabsd.ll9 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i)
20 ; CHECK-PWR8: vmaxsw
28 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub.i, <4 x i32> %a)
39 ; CHECK-PWR8: vmaxsw
311 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub, <4 x i32> %sub.i)
319 ; CHECK-PWR8: vmaxsw
359 declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>)
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs98 0x10,0x43,0x21,0x82 = vmaxsw 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s414 # CHECK-BE: vmaxsw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x82]
415 # CHECK-LE: vmaxsw 2, 3, 4 # encoding: [0x82,0x21,0x43,0x10]
416 vmaxsw 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s414 # CHECK-BE: vmaxsw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x82]
415 # CHECK-LE: vmaxsw 2, 3, 4 # encoding: [0x82,0x21,0x43,0x10]
416 vmaxsw 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt378 # CHECK: vmaxsw 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt378 # CHECK: vmaxsw 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td341 def int_ppc_altivec_vmaxsw : PowerPC_Vec_WWW_Intrinsic<"vmaxsw">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td415 def int_ppc_altivec_vmaxsw : PowerPC_Vec_WWW_Intrinsic<"vmaxsw">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2293 V(vmaxsw, VMAXSW, 0x10000182) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td570 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td571 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2589 __ vmaxsw(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4340 "vmaxsw\006vmaxub\006vmaxud\006vmaxuh\006vmaxuw\tvmhaddshs\nvmhraddshs\006"
6536 …{ 11022 /* vmaxsw */, PPC::VMAXSW, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, …
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc4845 ppc_altivec_vmaxsw, // llvm.ppc.altivec.vmaxsw
DIntrinsicImpl.inc4871 "llvm.ppc.altivec.vmaxsw",
13749 1, // llvm.ppc.altivec.vmaxsw
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3901 ppc_altivec_vmaxsw, // llvm.ppc.altivec.vmaxsw
9925 "llvm.ppc.altivec.vmaxsw",
17810 1, // llvm.ppc.altivec.vmaxsw
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3907 ppc_altivec_vmaxsw, // llvm.ppc.altivec.vmaxsw
9965 "llvm.ppc.altivec.vmaxsw",
17905 1, // llvm.ppc.altivec.vmaxsw
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3907 ppc_altivec_vmaxsw, // llvm.ppc.altivec.vmaxsw
9965 "llvm.ppc.altivec.vmaxsw",
17905 1, // llvm.ppc.altivec.vmaxsw
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3907 ppc_altivec_vmaxsw, // llvm.ppc.altivec.vmaxsw
9965 "llvm.ppc.altivec.vmaxsw",
17905 1, // llvm.ppc.altivec.vmaxsw
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3907 ppc_altivec_vmaxsw, // llvm.ppc.altivec.vmaxsw
9965 "llvm.ppc.altivec.vmaxsw",
17905 1, // llvm.ppc.altivec.vmaxsw