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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dlsr-post-inc-cross-use-offsets.ll104 %v45 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v41, <32 x i32> %v44)
109 %v50 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v45, <32 x i32> %v49)
119 %v60 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v56, <32 x i32> %v59)
124 %v65 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v60, <32 x i32> %v64)
125 %v66 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v50, <32 x i32> %v65)
135 %v76 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v72, <32 x i32> %v75)
140 %v81 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v76, <32 x i32> %v80)
141 %v82 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v66, <32 x i32> %v81)
167 %v104 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v99, <32 x i32> %v103)
172 %v109 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %v104, <32 x i32> %v108)
[all …]
Dhexagon_vector_loop_carried_reuse.ll3 ; CHECK: %.hexagon.vlcr = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B
52 …%14 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %a.sroa.0.058, <32 x i32> %b.sr…
53 %15 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %14, <32 x i32> %c.sroa.0.056)
54 %16 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %11, <32 x i32> %12)
55 %17 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %16, <32 x i32> %13)
71 declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1
Dhexagon_vector_loop_carried_reuse_constant.ll53 %15 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %14, <32 x i32> %c.sroa.0.056)
55 %17 = tail call <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32> %16, <32 x i32> %13)
71 declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1
Dlate_instr.ll124 %v97 = tail call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %v88, <16 x i32> %v90)
126 %v99 = tail call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %v94, <16 x i32> %v91)
129 %v102 = tail call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %v98, <16 x i32> %v100)
209 declare <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32>, <16 x i32>) #1
Dintrinsics-v60-alu.ll447 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %a, <16 x i32> %b)
970 declare <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32>, <16 x i32>) #0
Dv60Intrins.ll1009 %503 = call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %501, <16 x i32> %502)
2063 declare <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32>, <16 x i32>) #1
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs99 0x10,0x43,0x20,0x02 = vmaxub 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s420 # CHECK-BE: vmaxub 2, 3, 4 # encoding: [0x10,0x43,0x20,0x02]
421 # CHECK-LE: vmaxub 2, 3, 4 # encoding: [0x02,0x20,0x43,0x10]
422 vmaxub 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s420 # CHECK-BE: vmaxub 2, 3, 4 # encoding: [0x10,0x43,0x20,0x02]
421 # CHECK-LE: vmaxub 2, 3, 4 # encoding: [0x02,0x20,0x43,0x10]
422 vmaxub 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll840 declare i64 @llvm.hexagon.A2.vmaxub(i64, i64)
842 %z = call i64 @llvm.hexagon.A2.vmaxub(i64 %a, i64 %b)
845 ; CHECK: = vmaxub({{.*}},{{.*}})
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll840 declare i64 @llvm.hexagon.A2.vmaxub(i64, i64)
842 %z = call i64 @llvm.hexagon.A2.vmaxub(i64 %a, i64 %b)
845 ; CHECK: = vmaxub({{.*}}, {{.*}})
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt313 # CHECK: r17:16 = vmaxub(r21:20,r31:30)
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt313 # CHECK: r17:16 = vmaxub(r21:20, r31:30)
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt384 # CHECK: vmaxub 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt384 # CHECK: vmaxub 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td343 def int_ppc_altivec_vmaxub : PowerPC_Vec_BBB_Intrinsic<"vmaxub">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td417 def int_ppc_altivec_vmaxub : PowerPC_Vec_BBB_Intrinsic<"vmaxub">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2283 V(vmaxub, VMAXUB, 0x10000002) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td571 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td572 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepMappings.td313 def V6_vmaxub_altAlias : InstAlias<"$Vd32 = vmaxub($Vu32,$Vv32)", (V6_vmaxub HvxVR:$Vd32, HvxVR:$Vu…
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1366 hexagon_A2_vmaxub, // llvm.hexagon.A2.vmaxub
2559 hexagon_V6_vmaxub, // llvm.hexagon.V6.vmaxub
2560 hexagon_V6_vmaxub_128B, // llvm.hexagon.V6.vmaxub.128B
4846 ppc_altivec_vmaxub, // llvm.ppc.altivec.vmaxub
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2619 __ vmaxub(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/llvm/test/CodeGen/Hexagon/
Dv60Intrins.ll1010 %503 = call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %501, <16 x i32> %502)
2064 declare <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32>, <16 x i32>) #1
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4340 "vmaxsw\006vmaxub\006vmaxud\006vmaxuh\006vmaxuw\tvmhaddshs\nvmhraddshs\006"
6537 …{ 11029 /* vmaxub */, PPC::VMAXUB, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, …

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