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Searched refs:vmaxud (Results 1 – 20 of 20) sorted by relevance

/external/llvm/test/CodeGen/PowerPC/
Dvec_minmax.ll6 declare <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64>, <2 x i64>) nounwind readnone
17 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64> %x, <2 x i64> %y)
19 ; CHECK: vmaxud 2, 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvec_minmax.ll6 declare <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64>, <2 x i64>) nounwind readnone
17 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64> %x, <2 x i64> %y)
19 ; CHECK: vmaxud 2, 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s429 # CHECK-BE: vmaxud 2, 3, 4 # encoding: [0x10,0x43,0x20,0xc2]
430 # CHECK-LE: vmaxud 2, 3, 4 # encoding: [0xc2,0x20,0x43,0x10]
431 vmaxud 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s429 # CHECK-BE: vmaxud 2, 3, 4 # encoding: [0x10,0x43,0x20,0xc2]
430 # CHECK-LE: vmaxud 2, 3, 4 # encoding: [0xc2,0x20,0x43,0x10]
431 vmaxud 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt393 # CHECK: vmaxud 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt393 # CHECK: vmaxud 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td346 def int_ppc_altivec_vmaxud : PowerPC_Vec_DDD_Intrinsic<"vmaxud">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td420 def int_ppc_altivec_vmaxud : PowerPC_Vec_DDD_Intrinsic<"vmaxud">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2287 V(vmaxud, VMAXUD, 0x100000C2) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td1033 def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td1073 def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>;
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2594 __ vmaxud(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4340 "vmaxsw\006vmaxub\006vmaxud\006vmaxuh\006vmaxuw\tvmhaddshs\nvmhraddshs\006"
6538 …{ 11036 /* vmaxud */, PPC::VMAXUD, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, …
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc4847 ppc_altivec_vmaxud, // llvm.ppc.altivec.vmaxud
DIntrinsicImpl.inc4873 "llvm.ppc.altivec.vmaxud",
13751 1, // llvm.ppc.altivec.vmaxud
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3903 ppc_altivec_vmaxud, // llvm.ppc.altivec.vmaxud
9927 "llvm.ppc.altivec.vmaxud",
17812 1, // llvm.ppc.altivec.vmaxud
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3909 ppc_altivec_vmaxud, // llvm.ppc.altivec.vmaxud
9967 "llvm.ppc.altivec.vmaxud",
17907 1, // llvm.ppc.altivec.vmaxud
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3909 ppc_altivec_vmaxud, // llvm.ppc.altivec.vmaxud
9967 "llvm.ppc.altivec.vmaxud",
17907 1, // llvm.ppc.altivec.vmaxud
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3909 ppc_altivec_vmaxud, // llvm.ppc.altivec.vmaxud
9967 "llvm.ppc.altivec.vmaxud",
17907 1, // llvm.ppc.altivec.vmaxud
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3909 ppc_altivec_vmaxud, // llvm.ppc.altivec.vmaxud
9967 "llvm.ppc.altivec.vmaxud",
17907 1, // llvm.ppc.altivec.vmaxud