| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s.cs | 100 0x10,0x43,0x20,0x42 = vmaxuh 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 423 # CHECK-BE: vmaxuh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x42]
424 # CHECK-LE: vmaxuh 2, 3, 4 # encoding: [0x42,0x20,0x43,0x10]
425 vmaxuh 2, 3, 4
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 423 # CHECK-BE: vmaxuh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x42]
424 # CHECK-LE: vmaxuh 2, 3, 4 # encoding: [0x42,0x20,0x43,0x10]
425 vmaxuh 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | xtype_alu.ll | 862 declare i64 @llvm.hexagon.A2.vmaxuh(i64, i64)
864 %z = call i64 @llvm.hexagon.A2.vmaxuh(i64 %a, i64 %b)
867 ; CHECK: = vmaxuh({{.*}},{{.*}})
|
| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | xtype_alu.ll | 862 declare i64 @llvm.hexagon.A2.vmaxuh(i64, i64)
864 %z = call i64 @llvm.hexagon.A2.vmaxuh(i64 %a, i64 %b)
867 ; CHECK: = vmaxuh({{.*}}, {{.*}})
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Hexagon/ |
| D | xtype_alu.txt | 321 # CHECK: r17:16 = vmaxuh(r21:20,r31:30)
|
| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | xtype_alu.txt | 321 # CHECK: r17:16 = vmaxuh(r21:20, r31:30)
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 387 # CHECK: vmaxuh 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 387 # CHECK: vmaxuh 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | intrinsics-v60-alu.ll | 455 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmaxuh(<16 x i32> %a, <16 x i32> %b)
971 declare <16 x i32> @llvm.hexagon.V6.vmaxuh(<16 x i32>, <16 x i32>) #0
|
| D | v60Intrins.ll | 1063 %543 = call <16 x i32> @llvm.hexagon.V6.vmaxuh(<16 x i32> %541, <16 x i32> %542)
2105 declare <16 x i32> @llvm.hexagon.V6.vmaxuh(<16 x i32>, <16 x i32>) #1
|
| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsPowerPC.td | 344 def int_ppc_altivec_vmaxuh : PowerPC_Vec_HHH_Intrinsic<"vmaxuh">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | IntrinsicsPowerPC.td | 418 def int_ppc_altivec_vmaxuh : PowerPC_Vec_HHH_Intrinsic<"vmaxuh">;
|
| /external/v8/src/codegen/ppc/ |
| D | constants-ppc.h | 2291 V(vmaxuh, VMAXUH, 0x10000042) \
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 572 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 573 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonDepMappings.td | 314 def V6_vmaxuh_altAlias : InstAlias<"$Vd32 = vmaxuh($Vu32,$Vv32)", (V6_vmaxuh HvxVR:$Vd32, HvxVR:$Vu…
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1367 hexagon_A2_vmaxuh, // llvm.hexagon.A2.vmaxuh
2561 hexagon_V6_vmaxuh, // llvm.hexagon.V6.vmaxuh
2562 hexagon_V6_vmaxuh_128B, // llvm.hexagon.V6.vmaxuh.128B
4848 ppc_altivec_vmaxuh, // llvm.ppc.altivec.vmaxuh
|
| /external/v8/src/compiler/backend/ppc/ |
| D | code-generator-ppc.cc | 2609 __ vmaxuh(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
|
| /external/llvm/test/CodeGen/Hexagon/ |
| D | v60Intrins.ll | 1064 %543 = call <16 x i32> @llvm.hexagon.V6.vmaxuh(<16 x i32> %541, <16 x i32> %542)
2106 declare <16 x i32> @llvm.hexagon.V6.vmaxuh(<16 x i32>, <16 x i32>) #1
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 4340 "vmaxsw\006vmaxub\006vmaxud\006vmaxuh\006vmaxuw\tvmhaddshs\nvmhraddshs\006"
6539 …{ 11043 /* vmaxuh */, PPC::VMAXUH, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, …
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 821 hexagon_A2_vmaxuh, // llvm.hexagon.A2.vmaxuh
1873 hexagon_V6_vmaxuh, // llvm.hexagon.V6.vmaxuh
1874 hexagon_V6_vmaxuh_128B, // llvm.hexagon.V6.vmaxuh.128B
3904 ppc_altivec_vmaxuh, // llvm.ppc.altivec.vmaxuh
6845 "llvm.hexagon.A2.vmaxuh",
7897 "llvm.hexagon.V6.vmaxuh",
7898 "llvm.hexagon.V6.vmaxuh.128B",
9928 "llvm.ppc.altivec.vmaxuh",
14730 1, // llvm.hexagon.A2.vmaxuh
15782 1, // llvm.hexagon.V6.vmaxuh
[all …]
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 827 hexagon_A2_vmaxuh, // llvm.hexagon.A2.vmaxuh
1879 hexagon_V6_vmaxuh, // llvm.hexagon.V6.vmaxuh
1880 hexagon_V6_vmaxuh_128B, // llvm.hexagon.V6.vmaxuh.128B
3910 ppc_altivec_vmaxuh, // llvm.ppc.altivec.vmaxuh
6885 "llvm.hexagon.A2.vmaxuh",
7937 "llvm.hexagon.V6.vmaxuh",
7938 "llvm.hexagon.V6.vmaxuh.128B",
9968 "llvm.ppc.altivec.vmaxuh",
14825 1, // llvm.hexagon.A2.vmaxuh
15877 1, // llvm.hexagon.V6.vmaxuh
[all …]
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 827 hexagon_A2_vmaxuh, // llvm.hexagon.A2.vmaxuh
1879 hexagon_V6_vmaxuh, // llvm.hexagon.V6.vmaxuh
1880 hexagon_V6_vmaxuh_128B, // llvm.hexagon.V6.vmaxuh.128B
3910 ppc_altivec_vmaxuh, // llvm.ppc.altivec.vmaxuh
6885 "llvm.hexagon.A2.vmaxuh",
7937 "llvm.hexagon.V6.vmaxuh",
7938 "llvm.hexagon.V6.vmaxuh.128B",
9968 "llvm.ppc.altivec.vmaxuh",
14825 1, // llvm.hexagon.A2.vmaxuh
15877 1, // llvm.hexagon.V6.vmaxuh
[all …]
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 827 hexagon_A2_vmaxuh, // llvm.hexagon.A2.vmaxuh
1879 hexagon_V6_vmaxuh, // llvm.hexagon.V6.vmaxuh
1880 hexagon_V6_vmaxuh_128B, // llvm.hexagon.V6.vmaxuh.128B
3910 ppc_altivec_vmaxuh, // llvm.ppc.altivec.vmaxuh
6885 "llvm.hexagon.A2.vmaxuh",
7937 "llvm.hexagon.V6.vmaxuh",
7938 "llvm.hexagon.V6.vmaxuh.128B",
9968 "llvm.ppc.altivec.vmaxuh",
14825 1, // llvm.hexagon.A2.vmaxuh
15877 1, // llvm.hexagon.V6.vmaxuh
[all …]
|