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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/
Dv62a.s9 r19:18,p3=vminub(r17:16, r15:14)
10 # CHECK: eaeed072 { r19:18,p3 = vminub(r17:16,r15:14)
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs105 0x10,0x43,0x22,0x02 = vminub 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dlate_instr.ll125 %v98 = tail call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %v88, <16 x i32> %v90)
127 %v100 = tail call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %v94, <16 x i32> %v91)
128 %v101 = tail call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %v97, <16 x i32> %v99)
212 declare <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32>, <16 x i32>) #1
Dintrinsics-v60-alu.ll415 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %a, <16 x i32> %b)
966 declare <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32>, <16 x i32>) #0
Dv60Intrins.ll1013 %506 = call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %504, <16 x i32> %505)
2066 declare <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32>, <16 x i32>) #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s445 # CHECK-BE: vminub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x02]
446 # CHECK-LE: vminub 2, 3, 4 # encoding: [0x02,0x22,0x43,0x10]
447 vminub 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s445 # CHECK-BE: vminub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x02]
446 # CHECK-LE: vminub 2, 3, 4 # encoding: [0x02,0x22,0x43,0x10]
447 vminub 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll900 declare i64 @llvm.hexagon.A2.vminub(i64, i64)
902 %z = call i64 @llvm.hexagon.A2.vminub(i64 %a, i64 %b)
905 ; CHECK: = vminub({{.*}},{{.*}})
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll900 declare i64 @llvm.hexagon.A2.vminub(i64, i64)
902 %z = call i64 @llvm.hexagon.A2.vminub(i64 %a, i64 %b)
905 ; CHECK: = vminub({{.*}}, {{.*}})
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt343 # CHECK: r17:16 = vminub(r21:20,r31:30)
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt343 # CHECK: r17:16 = vminub(r21:20, r31:30)
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt408 # CHECK: vminub 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt408 # CHECK: vminub 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td354 def int_ppc_altivec_vminub : PowerPC_Vec_BBB_Intrinsic<"vminub">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td428 def int_ppc_altivec_vminub : PowerPC_Vec_BBB_Intrinsic<"vminub">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2299 V(vminub, VMINUB, 0x10000202) \
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2579 __ vminub(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
3237 __ vminub(tempFPReg2, src1, tempFPReg2); in AssembleArchInstruction() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td578 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td579 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepMappings.td318 def V6_vminub_altAlias : InstAlias<"$Vd32 = vminub($Vu32,$Vv32)", (V6_vminub HvxVR:$Vd32, HvxVR:$Vu…
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1372 hexagon_A2_vminub, // llvm.hexagon.A2.vminub
2569 hexagon_V6_vminub, // llvm.hexagon.V6.vminub
2570 hexagon_V6_vminub_128B, // llvm.hexagon.V6.vminub.128B
4857 ppc_altivec_vminub, // llvm.ppc.altivec.vminub
/external/llvm/test/CodeGen/Hexagon/
Dv60Intrins.ll1014 %506 = call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %504, <16 x i32> %505)
2067 declare <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32>, <16 x i32>) #1
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4341 "vminfp\006vminsb\006vminsd\006vminsh\006vminsw\006vminub\006vminud\006v"
6548 …{ 11113 /* vminub */, PPC::VMINUB, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, …
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen826 hexagon_A2_vminub, // llvm.hexagon.A2.vminub
1879 hexagon_V6_vminub, // llvm.hexagon.V6.vminub
1880 hexagon_V6_vminub_128B, // llvm.hexagon.V6.vminub.128B
3913 ppc_altivec_vminub, // llvm.ppc.altivec.vminub
6850 "llvm.hexagon.A2.vminub",
7903 "llvm.hexagon.V6.vminub",
7904 "llvm.hexagon.V6.vminub.128B",
9937 "llvm.ppc.altivec.vminub",
14735 1, // llvm.hexagon.A2.vminub
15788 1, // llvm.hexagon.V6.vminub
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen832 hexagon_A2_vminub, // llvm.hexagon.A2.vminub
1885 hexagon_V6_vminub, // llvm.hexagon.V6.vminub
1886 hexagon_V6_vminub_128B, // llvm.hexagon.V6.vminub.128B
3919 ppc_altivec_vminub, // llvm.ppc.altivec.vminub
6890 "llvm.hexagon.A2.vminub",
7943 "llvm.hexagon.V6.vminub",
7944 "llvm.hexagon.V6.vminub.128B",
9977 "llvm.ppc.altivec.vminub",
14830 1, // llvm.hexagon.A2.vminub
15883 1, // llvm.hexagon.V6.vminub
[all …]

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