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Searched refs:vminud (Results 1 – 20 of 20) sorted by relevance

/external/llvm/test/CodeGen/PowerPC/
Dvec_minmax.ll8 declare <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64>, <2 x i64>) nounwind readnone
29 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64> %x, <2 x i64> %y)
31 ; CHECK: vminud 2, 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvec_minmax.ll8 declare <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64>, <2 x i64>) nounwind readnone
29 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64> %x, <2 x i64> %y)
31 ; CHECK: vminud 2, 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s454 # CHECK-BE: vminud 2, 3, 4 # encoding: [0x10,0x43,0x22,0xc2]
455 # CHECK-LE: vminud 2, 3, 4 # encoding: [0xc2,0x22,0x43,0x10]
456 vminud 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s454 # CHECK-BE: vminud 2, 3, 4 # encoding: [0x10,0x43,0x22,0xc2]
455 # CHECK-LE: vminud 2, 3, 4 # encoding: [0xc2,0x22,0x43,0x10]
456 vminud 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt417 # CHECK: vminud 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt417 # CHECK: vminud 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td357 def int_ppc_altivec_vminud : PowerPC_Vec_DDD_Intrinsic<"vminud">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td431 def int_ppc_altivec_vminud : PowerPC_Vec_DDD_Intrinsic<"vminud">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2303 V(vminud, VMINUD, 0x100002C2) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td1035 def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td1075 def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2554 __ vminud(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4341 "vminfp\006vminsb\006vminsd\006vminsh\006vminsw\006vminub\006vminud\006v"
6549 …{ 11120 /* vminud */, PPC::VMINUD, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, …
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc4858 ppc_altivec_vminud, // llvm.ppc.altivec.vminud
DIntrinsicImpl.inc4884 "llvm.ppc.altivec.vminud",
13762 1, // llvm.ppc.altivec.vminud
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3914 ppc_altivec_vminud, // llvm.ppc.altivec.vminud
9938 "llvm.ppc.altivec.vminud",
17823 1, // llvm.ppc.altivec.vminud
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3920 ppc_altivec_vminud, // llvm.ppc.altivec.vminud
9978 "llvm.ppc.altivec.vminud",
17918 1, // llvm.ppc.altivec.vminud
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3920 ppc_altivec_vminud, // llvm.ppc.altivec.vminud
9978 "llvm.ppc.altivec.vminud",
17918 1, // llvm.ppc.altivec.vminud
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3920 ppc_altivec_vminud, // llvm.ppc.altivec.vminud
9978 "llvm.ppc.altivec.vminud",
17918 1, // llvm.ppc.altivec.vminud
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3920 ppc_altivec_vminud, // llvm.ppc.altivec.vminud
9978 "llvm.ppc.altivec.vminud",
17918 1, // llvm.ppc.altivec.vminud