Home
last modified time | relevance | path

Searched refs:vminuh (Results 1 – 25 of 30) sorted by relevance

12

/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs106 0x10,0x43,0x22,0x42 = vminuh 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dreg-scavengebug.ll87 %v56 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %v55, <16 x i32> %v8)
152 %v118 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %v117, <16 x i32> %v8)
183 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
Dintrinsics-v60-alu.ll423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b)
967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
Dv60Intrins.ll1067 %546 = call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %544, <16 x i32> %545)
2108 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s448 # CHECK-BE: vminuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x42]
449 # CHECK-LE: vminuh 2, 3, 4 # encoding: [0x42,0x22,0x43,0x10]
450 vminuh 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s448 # CHECK-BE: vminuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x42]
449 # CHECK-LE: vminuh 2, 3, 4 # encoding: [0x42,0x22,0x43,0x10]
450 vminuh 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll922 declare i64 @llvm.hexagon.A2.vminuh(i64, i64)
924 %z = call i64 @llvm.hexagon.A2.vminuh(i64 %a, i64 %b)
927 ; CHECK: = vminuh({{.*}},{{.*}})
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll922 declare i64 @llvm.hexagon.A2.vminuh(i64, i64)
924 %z = call i64 @llvm.hexagon.A2.vminuh(i64 %a, i64 %b)
927 ; CHECK: = vminuh({{.*}}, {{.*}})
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt351 # CHECK: r17:16 = vminuh(r21:20,r31:30)
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt351 # CHECK: r17:16 = vminuh(r21:20, r31:30)
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt411 # CHECK: vminuh 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt411 # CHECK: vminuh 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td355 def int_ppc_altivec_vminuh : PowerPC_Vec_HHH_Intrinsic<"vminuh">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td429 def int_ppc_altivec_vminuh : PowerPC_Vec_HHH_Intrinsic<"vminuh">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2307 V(vminuh, VMINUH, 0x10000242) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td579 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td580 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepMappings.td319 def V6_vminuh_altAlias : InstAlias<"$Vd32 = vminuh($Vu32,$Vv32)", (V6_vminuh HvxVR:$Vd32, HvxVR:$Vu…
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1373 hexagon_A2_vminuh, // llvm.hexagon.A2.vminuh
2571 hexagon_V6_vminuh, // llvm.hexagon.V6.vminuh
2572 hexagon_V6_vminuh_128B, // llvm.hexagon.V6.vminuh.128B
4859 ppc_altivec_vminuh, // llvm.ppc.altivec.vminuh
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2569 __ vminuh(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/llvm/test/CodeGen/Hexagon/
Dv60Intrins.ll1068 %546 = call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %544, <16 x i32> %545)
2109 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #1
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen827 hexagon_A2_vminuh, // llvm.hexagon.A2.vminuh
1881 hexagon_V6_vminuh, // llvm.hexagon.V6.vminuh
1882 hexagon_V6_vminuh_128B, // llvm.hexagon.V6.vminuh.128B
3915 ppc_altivec_vminuh, // llvm.ppc.altivec.vminuh
6851 "llvm.hexagon.A2.vminuh",
7905 "llvm.hexagon.V6.vminuh",
7906 "llvm.hexagon.V6.vminuh.128B",
9939 "llvm.ppc.altivec.vminuh",
14736 1, // llvm.hexagon.A2.vminuh
15790 1, // llvm.hexagon.V6.vminuh
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen833 hexagon_A2_vminuh, // llvm.hexagon.A2.vminuh
1887 hexagon_V6_vminuh, // llvm.hexagon.V6.vminuh
1888 hexagon_V6_vminuh_128B, // llvm.hexagon.V6.vminuh.128B
3921 ppc_altivec_vminuh, // llvm.ppc.altivec.vminuh
6891 "llvm.hexagon.A2.vminuh",
7945 "llvm.hexagon.V6.vminuh",
7946 "llvm.hexagon.V6.vminuh.128B",
9979 "llvm.ppc.altivec.vminuh",
14831 1, // llvm.hexagon.A2.vminuh
15885 1, // llvm.hexagon.V6.vminuh
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen833 hexagon_A2_vminuh, // llvm.hexagon.A2.vminuh
1887 hexagon_V6_vminuh, // llvm.hexagon.V6.vminuh
1888 hexagon_V6_vminuh_128B, // llvm.hexagon.V6.vminuh.128B
3921 ppc_altivec_vminuh, // llvm.ppc.altivec.vminuh
6891 "llvm.hexagon.A2.vminuh",
7945 "llvm.hexagon.V6.vminuh",
7946 "llvm.hexagon.V6.vminuh.128B",
9979 "llvm.ppc.altivec.vminuh",
14831 1, // llvm.hexagon.A2.vminuh
15885 1, // llvm.hexagon.V6.vminuh
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen833 hexagon_A2_vminuh, // llvm.hexagon.A2.vminuh
1887 hexagon_V6_vminuh, // llvm.hexagon.V6.vminuh
1888 hexagon_V6_vminuh_128B, // llvm.hexagon.V6.vminuh.128B
3921 ppc_altivec_vminuh, // llvm.ppc.altivec.vminuh
6891 "llvm.hexagon.A2.vminuh",
7945 "llvm.hexagon.V6.vminuh",
7946 "llvm.hexagon.V6.vminuh.128B",
9979 "llvm.ppc.altivec.vminuh",
14831 1, // llvm.hexagon.A2.vminuh
15885 1, // llvm.hexagon.V6.vminuh
[all …]

12