| /external/llvm/test/CodeGen/PowerPC/ |
| D | vec_cmp.ll | 57 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
67 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
77 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
123 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
133 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
183 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
193 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
203 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
249 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
259 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
[all …]
|
| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s.cs | 128 0x10,0x43,0x25,0x04 = vnor 2, 3, 4
|
| /external/v8/src/compiler/backend/ppc/ |
| D | code-generator-ppc.cc | 2631 __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); in AssembleArchInstruction() local
2672 __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); in AssembleArchInstruction() local
2678 __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); in AssembleArchInstruction() local
2684 __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); in AssembleArchInstruction() local
2690 __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); in AssembleArchInstruction() local
2696 __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); in AssembleArchInstruction() local
2905 __ vnor(dst, src, src); in AssembleArchInstruction() local
2962 __ vnor(tempFPReg1, i.InputSimd128Register(0), i.InputSimd128Register(0)); in AssembleArchInstruction() local
2971 __ vnor(tempFPReg1, i.InputSimd128Register(0), i.InputSimd128Register(0)); in AssembleArchInstruction() local
2992 __ vnor(tempFPReg1, i.InputSimd128Register(0), i.InputSimd128Register(0)); in AssembleArchInstruction() local
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 550 # CHECK-BE: vnor 2, 3, 4 # encoding: [0x10,0x43,0x25,0x04]
551 # CHECK-LE: vnor 2, 3, 4 # encoding: [0x04,0x25,0x43,0x10]
552 vnor 2, 3, 4
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 550 # CHECK-BE: vnor 2, 3, 4 # encoding: [0x10,0x43,0x25,0x04]
551 # CHECK-LE: vnor 2, 3, 4 # encoding: [0x04,0x25,0x43,0x10]
552 vnor 2, 3, 4
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 507 # CHECK: vnor 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 507 # CHECK: vnor 2, 3, 4
|
| /external/v8/src/codegen/ppc/ |
| D | constants-ppc.h | 2239 V(vnor, VNOR, 0x10000504) \
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 674 "vnor $vD, $vA, $vB", IIC_VecFP,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 675 "vnor $vD, $vA, $vB", IIC_VecFP,
|
| /external/llvm/test/CodeGen/Hexagon/ |
| D | v60Intrins.ll | 170 ; CHECK: v{{[0-9]*}}.h = vnor{{[0-9]*}}mamt(v{{[0-9]*}}.h)
259 ; CHECK: v{{[0-9]*}}.w = vnor{{[0-9]*}}mamt(v{{[0-9]*}}.w)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | v60Intrins.ll | 169 ; CHECK: v{{[0-9]*}}.h = vnor{{[0-9]*}}mamt(v{{[0-9]*}}.h)
258 ; CHECK: v{{[0-9]*}}.w = vnor{{[0-9]*}}mamt(v{{[0-9]*}}.w)
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 4348 "gw\010vnmsubfp\004vnor\004vnot\003vor\004vorc\005vperm\006vpermr\010vpe"
6591 …{ 11458 /* vnor */, PPC::VNOR, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, MCK_…
|