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Searched refs:vpkswss (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/CodeGen/PowerPC/
Dpr26193.ll4 %0 = tail call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %a, <4 x i32> %a)
7 ; CHECK: vpkswss 2,
9 declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dpr26193.ll4 %0 = tail call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %a, <4 x i32> %a)
7 ; CHECK: vpkswss 2,
9 declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>)
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs17 0x10,0x43,0x21,0xce = vpkswss 2, 3, 4
/external/mesa3d/docs/relnotes/
D11.0.9.rst94 - llvmpipe: use vpkswss when dst is signed
D11.1.3.rst224 - llvmpipe: use vpkswss when dst is signed
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s57 # CHECK-BE: vpkswss 2, 3, 4 # encoding: [0x10,0x43,0x21,0xce]
58 # CHECK-LE: vpkswss 2, 3, 4 # encoding: [0xce,0x21,0x43,0x10]
59 vpkswss 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s57 # CHECK-BE: vpkswss 2, 3, 4 # encoding: [0x10,0x43,0x21,0xce]
58 # CHECK-LE: vpkswss 2, 3, 4 # encoding: [0xce,0x21,0x43,0x10]
59 vpkswss 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt48 # CHECK: vpkswss 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt48 # CHECK: vpkswss 2, 3, 4
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2339 V(vpkswss, VPKSWSS, 0x100001CE) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td738 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td745 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc3150 __ vpkswss(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4349 "rmxor\005vpkpx\007vpksdss\007vpksdus\007vpkshss\007vpkshus\007vpkswss\007"
6603 …{ 11537 /* vpkswss */, PPC::VPKSWSS, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC…
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc4887 ppc_altivec_vpkswss, // llvm.ppc.altivec.vpkswss
DIntrinsicImpl.inc4913 "llvm.ppc.altivec.vpkswss",
13791 1, // llvm.ppc.altivec.vpkswss
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3943 ppc_altivec_vpkswss, // llvm.ppc.altivec.vpkswss
9967 "llvm.ppc.altivec.vpkswss",
17852 1, // llvm.ppc.altivec.vpkswss
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3949 ppc_altivec_vpkswss, // llvm.ppc.altivec.vpkswss
10007 "llvm.ppc.altivec.vpkswss",
17947 1, // llvm.ppc.altivec.vpkswss
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3949 ppc_altivec_vpkswss, // llvm.ppc.altivec.vpkswss
10007 "llvm.ppc.altivec.vpkswss",
17947 1, // llvm.ppc.altivec.vpkswss
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3949 ppc_altivec_vpkswss, // llvm.ppc.altivec.vpkswss
10007 "llvm.ppc.altivec.vpkswss",
17947 1, // llvm.ppc.altivec.vpkswss
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3949 ppc_altivec_vpkswss, // llvm.ppc.altivec.vpkswss
10007 "llvm.ppc.altivec.vpkswss",
17947 1, // llvm.ppc.altivec.vpkswss