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Searched refs:vreg (Results 1 – 25 of 106) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Darm64-ldp-cluster.ll9 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
10 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
14 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
15 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
29 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
30 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
34 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
35 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
50 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDURWi
51 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDURWi
[all …]
Dtailcall_misched_graph.ll29 ; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
30 ; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
31 ; CHECK: STRXui %vreg{{.*}}, <fi#-4>
43 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4>
44 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>
Darm64-fast-isel-rem.ll7 ; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
9 ; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
/external/v8/src/compiler/backend/
Dspill-placer.h100 int GetOrCreateIndexForLatestVreg(int vreg);
102 bool IsLatestVreg(int vreg) const { in IsLatestVreg() argument
104 vreg_numbers_[assigned_indices_ - 1] == vreg; in IsLatestVreg()
118 void SetSpillRequired(InstructionBlock* block, int vreg,
121 void SetDefinition(RpoNumber block, int vreg);
137 void CommitSpill(int vreg, InstructionBlock* predecessor,
Dspill-placer.cc69 DCHECK(!IsLatestVreg(range->vreg())); in Add()
82 SetSpillRequired(code->InstructionBlockAt(start_block), range->vreg(), in Add()
100 DCHECK(!IsLatestVreg(range->vreg())); in Add()
103 SetSpillRequired(block, range->vreg(), top_start_block_number); in Add()
110 if (!IsLatestVreg(range->vreg())) { in Add()
115 SetDefinition(top_start_block_number, range->vreg()); in Add()
205 int SpillPlacer::GetOrCreateIndexForLatestVreg(int vreg) { in GetOrCreateIndexForLatestVreg() argument
208 if (!IsLatestVreg(vreg)) { in GetOrCreateIndexForLatestVreg()
228 vreg_numbers_[assigned_indices_] = vreg; in GetOrCreateIndexForLatestVreg()
264 void SpillPlacer::SetSpillRequired(InstructionBlock* block, int vreg, in SetSpillRequired() argument
[all …]
Dregister-allocator-verifier.h98 bool IsAliasOf(int vreg) const { return aliases_.count(vreg) > 0; } in IsAliasOf() argument
99 void AddAlias(int vreg) { aliases_.insert(vreg); } in AddAlias() argument
251 void AddDelayedAssessment(InstructionOperand op, int vreg) { in AddDelayedAssessment() argument
254 map_.insert(std::make_pair(op, vreg)); in AddDelayedAssessment()
256 CHECK_EQ(it->second, vreg); in AddDelayedAssessment()
Dregister-allocator.cc693 if (pos == other_pos) return TopLevel()->vreg() < other->TopLevel()->vreg(); in ShouldBeAllocatedBefore()
698 return TopLevel()->vreg() < other->TopLevel()->vreg(); in ShouldBeAllocatedBefore()
814 TopLevelLiveRange::TopLevelLiveRange(int vreg, MachineRepresentation rep) in TopLevelLiveRange() argument
816 vreg_(vreg), in TopLevelLiveRange()
954 TRACE_COND(trace_alloc, "Shorten live range %d to [%d\n", vreg(), in ShortenTo()
965 TRACE_COND(trace_alloc, "Ensure live range %d in interval [%d %d[\n", vreg(), in EnsureInterval()
986 TRACE_COND(trace_alloc, "Add to live range %d interval [%d %d[\n", vreg(), in AddUseInterval()
1012 TRACE_COND(trace_alloc, "Add to live range %d use position %d\n", vreg(), in AddUsePosition()
1057 os << "Range: " << range->TopLevel()->vreg() << ":" << range->relative_id() in operator <<()
1111 os << std::setw(3) << toplevel->vreg() << ": "; in PrintRangeRow()
[all …]
Dregister-allocator-verifier.cc161 int vreg = unallocated->virtual_register(); in BuildConstraint() local
162 constraint->virtual_register_ = vreg; in BuildConstraint()
170 if (sequence()->IsFP(vreg)) { in BuildConstraint()
177 DCHECK(!sequence()->IsFP(vreg)); in BuildConstraint()
194 if (sequence()->IsFP(vreg)) { in BuildConstraint()
203 ElementSizeLog2Of(sequence()->GetRepresentation(vreg)); in BuildConstraint()
598 int vreg = pair.second; in VerifyGapMoves() local
607 vreg); in VerifyGapMoves()
612 vreg); in VerifyGapMoves()
Dinstruction-selector-impl.h226 InstructionOperand DefineSameAsFirstForVreg(int vreg) { in DefineSameAsFirstForVreg() argument
227 return UnallocatedOperand(UnallocatedOperand::SAME_AS_FIRST_INPUT, vreg); in DefineSameAsFirstForVreg()
230 InstructionOperand DefineAsRegistertForVreg(int vreg) { in DefineAsRegistertForVreg() argument
231 return UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg); in DefineAsRegistertForVreg()
234 InstructionOperand UseRegisterForVreg(int vreg) { in UseRegisterForVreg() argument
236 UnallocatedOperand::USED_AT_START, vreg); in UseRegisterForVreg()
/external/bcc/src/lua/bpf/
Dbuiltins.lua79 e.emit(BPF.ALU + BPF.END + BPF.TO_BE, e.vreg(dst), 0, 0, w)
87 e.emit(BPF.ALU + BPF.END + BPF.TO_LE, e.vreg(dst), 0, 0, w)
114 local src_reg = e.vreg(b)
115 local dst_reg = e.vreg(a)
118 e.vreg(ret, 0, true, ffi.typeof('int32_t'))
152 e.vreg(src, 3)
161 e.vreg(ret, 0, true, ffi.typeof('int32_t'))
227 e.vreg(src, 3)
232 e.vreg(ret, 0, true, ffi.typeof('int32_t'))
271 e.vreg(e.tmpvar, 3+i-1) -- Materialize it in arg register
[all …]
Dbpf.lua197 local function vreg(var, reg, reserve, vtype) function
300 src_reg = vreg(a)
307 src_reg = vreg(a)
316 src_reg = vreg(a)
330 vreg(i)
337 vreg(i, Vcomp[i].reg)
383 local a_reg, b_reg = vreg(a), vreg(b)
410 local reg = vreg(a)
440 local dst_reg = vreg(dst)
460 local src_reg = b and vreg(b) or 0 -- SRC is optional for unary operations
[all …]
Dproto.lua229 dst_reg = e.vreg(var, 0, true)
233 tmp_reg = e.vreg(e.tmpvar, 0, true, type) -- Reserve R0 for temporary relative offset
234 dst_reg = e.vreg(var) -- Must rematerialize (if it was spilled by tmp var)
263 local dst_reg = e.vreg(var)
/external/v8/src/execution/arm64/
Dsimulator-arm64.cc1285 ? vreg(code).Get<float>(lane) in PrintVRegisterFPHelper()
1286 : vreg(code).Get<double>(lane); in PrintVRegisterFPHelper()
2927 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing1Source()
2928 SimVRegister& rn = vreg(instr->Rn()); in VisitFPDataProcessing1Source()
2943 fabs_(vform, vreg(fd), vreg(fn)); in VisitFPDataProcessing1Source()
2949 fneg(vform, vreg(fd), vreg(fn)); in VisitFPDataProcessing1Source()
3018 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing2Source()
3019 SimVRegister& rn = vreg(instr->Rn()); in VisitFPDataProcessing2Source()
3020 SimVRegister& rm = vreg(instr->Rm()); in VisitFPDataProcessing2Source()
3696 SimVRegister& rd = vreg(instr->Rd()); in VisitNEON2RegMisc()
[all …]
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_finalize.cpp516 unsigned vreg = v->gpr.sel(); in copy_fetch_src() local
520 reg = vreg; in copy_fetch_src()
521 else if ((unsigned)reg != vreg) { in copy_fetch_src()
623 unsigned vreg = v->gpr.sel(); in finalize_fetch() local
627 reg = vreg; in finalize_fetch()
628 else if ((unsigned)reg != vreg) { in finalize_fetch()
670 unsigned vreg = v->gpr.sel(); in finalize_fetch() local
674 reg = vreg; in finalize_fetch()
675 else if ((unsigned)reg != vreg) { in finalize_fetch()
747 unsigned vreg = v->gpr.sel(); in finalize_cf() local
[all …]
/external/v8/src/codegen/x64/
Dassembler-x64-inl.h187 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument
193 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix()
196 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix()
200 void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm, in emit_vex_prefix() argument
204 XMMRegister ivreg = XMMRegister::from_code(vreg.code()); in emit_vex_prefix()
209 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, Operand rm, in emit_vex_prefix() argument
215 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix()
218 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix()
222 void Assembler::emit_vex_prefix(Register reg, Register vreg, Operand rm, in emit_vex_prefix() argument
226 XMMRegister ivreg = XMMRegister::from_code(vreg.code()); in emit_vex_prefix()
/external/llvm/test/CodeGen/PowerPC/
Dquadint-return.ll17 ; CHECK: %X3<def> = COPY %vreg
18 ; CHECK-NEXT: %X4<def> = COPY %vreg
/external/u-boot/board/compulab/cm_t54/
Dcm_t54.c55 static int cm_t54_palmas_regulator_set(u8 vreg, u8 vval, u8 creg, u8 cval) in cm_t54_palmas_regulator_set() argument
60 err = palmas_i2c_write_u8(TWL603X_CHIP_P1, vreg, vval); in cm_t54_palmas_regulator_set()
63 vreg, err); in cm_t54_palmas_regulator_set()
/external/llvm/test/CodeGen/ARM/
Dmisched-copy-arm.ll36 ; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
37 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]]
38 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
Dfast-isel-shift-materialize.ll6 ; When materializing the '2' for the shifts below, the second shift kills the vreg
7 ; we materialize in to. However, the first shift was also killing that vreg.
Dfast-isel-remat-same-constant.ll7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou…
9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
/external/arm-optimized-routines/string/arm/
Dmemcpy.S85 .macro cpy_line_vfp vreg, base
86 vstr \vreg, [dst, #\base]
87 vldr \vreg, [src, #\base]
94 vstr \vreg, [dst, #\base + 32]
95 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
104 .macro cpy_tail_vfp vreg, base
105 vstr \vreg, [dst, #\base]
106 vldr \vreg, [src, #\base]
113 vstr \vreg, [dst, #\base + 32]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfast-isel-shift-materialize.ll6 ; When materializing the '2' for the shifts below, the second shift kills the vreg
7 ; we materialize in to. However, the first shift was also killing that vreg.
Dfast-isel-remat-same-constant.ll7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou…
9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
/external/v8/src/compiler/
Dgraph-visualizer.cc447 void PrintLiveRange(const LiveRange* range, const char* type, int vreg);
734 int vreg = range->vreg(); in PrintLiveRangeChain() local
737 PrintLiveRange(child, type, vreg); in PrintLiveRangeChain()
742 int vreg) { in PrintLiveRange() argument
745 os_ << vreg << ":" << range->relative_id() << " " << type; in PrintLiveRange()
778 os_ << " " << parent->vreg() << ":" << parent->relative_id(); in PrintLiveRange()
1029 int vreg = top_level_live_range_json.range_.vreg(); in operator <<() local
1031 os << "\"" << (vreg > 0 ? vreg : -vreg) << "\":{ \"child_ranges\":["; in operator <<()
1149 int vreg = ConstantOperand::cast(op)->virtual_register(); in operator <<() local
1151 os << "\"text\": \"v" << vreg << "\","; in operator <<()
[all …]
/external/vixl/test/aarch64/
Dtest-utils-aarch64.cc210 const VRegister& vreg) { in Equal128() argument
211 VIXL_ASSERT(vreg.Is128Bits()); in Equal128()
213 vec128_t result = core->qreg(vreg.GetCode()); in Equal128()
286 const VRegister& vreg) { in Equal64() argument
287 VIXL_ASSERT(vreg.Is64Bits()); in Equal64()
288 uint64_t result = core->dreg_bits(vreg.GetCode()); in Equal64()

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