| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s.cs | 36 0x10,0x41,0x1a,0x4c = vsplth 2, 3, 1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | vsx-partword-int-loads-and-stores.ll | 29 ; CHECK-NEXT: vsplth 2, 2, 3
32 ; CHECK-BE-NEXT: vsplth 2, 2, 3
92 ; CHECK-NEXT: vsplth 2, 2, 3
95 ; CHECK-BE-NEXT: vsplth 2, 2, 3
338 ; CHECK-NEXT: vsplth 2, 2, 3
341 ; CHECK-BE-NEXT: vsplth 2, 2, 3
402 ; CHECK-NEXT: vsplth 2, 2, 3
405 ; CHECK-BE-NEXT: vsplth 2, 2, 3
|
| D | swaps-le-2.ll | 92 ; CHECK: vsplth {{[0-9]+}}, {{[0-9]+}}, 5
|
| D | vec_splat.ll | 7 ; RUN: grep vsplth %t | count 1
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | swaps-le-2.ll | 85 ; CHECK: vsplth {{[0-9]+}}, {{[0-9]+}}, 5
|
| D | vec_splat.ll | 7 ; RUN: grep vsplth %t | count 1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 123 # CHECK-BE: vsplth 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x4c]
124 # CHECK-LE: vsplth 2, 3, 1 # encoding: [0x4c,0x1a,0x41,0x10]
125 vsplth 2, 3, 1
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 123 # CHECK-BE: vsplth 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x4c]
124 # CHECK-LE: vsplth 2, 3, 1 # encoding: [0x4c,0x1a,0x41,0x10]
125 vsplth 2, 3, 1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | Lexicon.rst | 274 this functionality in hardware. For example, "vsplth" and the corresponding
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 111 # CHECK: vsplth 2, 3, 1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 111 # CHECK: vsplth 2, 3, 1
|
| /external/v8/src/compiler/backend/ppc/ |
| D | code-generator-ppc.cc | 2272 __ vsplth(dst, dst, Operand(3)); in AssembleArchInstruction() local
2991 __ vsplth(kScratchDoubleReg, kScratchDoubleReg, Operand(3)); in AssembleArchInstruction() local
3134 __ vsplth(kScratchDoubleReg, kScratchDoubleReg, Operand(3)); in AssembleArchInstruction() local
3144 __ vsplth(kScratchDoubleReg, kScratchDoubleReg, Operand(3)); in AssembleArchInstruction() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 703 "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
714 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>;
|
| /external/v8/src/codegen/ppc/ |
| D | constants-ppc.h | 2215 V(vsplth, VSPLTH, 0x1000024C) \
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 702 "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 4356 "slw\006vspltb\006vsplth\010vspltisb\010vspltish\010vspltisw\006vspltw\003"
6649 …{ 11862 /* vsplth */, PPC::VSPLTH, Convert__RegVRRC1_0__U5Imm1_2__RegVRRC1_1, 0, { MCK_RegVRRC, MC…
|