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Searched refs:vsro (Results 1 – 20 of 20) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dshift128.ll69 ; P8-NOT: {{\b}}vsro
71 ; P9-DAG: vsro
88 ; CHECK-NOT: {{\b}}vsro
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs47 0x10,0x43,0x24,0x4c = vsro 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s207 # CHECK-BE: vsro 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4c]
208 # CHECK-LE: vsro 2, 3, 4 # encoding: [0x4c,0x24,0x43,0x10]
209 vsro 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s207 # CHECK-BE: vsro 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4c]
208 # CHECK-LE: vsro 2, 3, 4 # encoding: [0x4c,0x24,0x43,0x10]
209 vsro 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt180 # CHECK: vsro 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt180 # CHECK: vsro 2, 3, 4
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td583 def int_ppc_altivec_vsro : PowerPC_Vec_WWW_Intrinsic<"vsro">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td659 def int_ppc_altivec_vsro : PowerPC_Vec_WWW_Intrinsic<"vsro">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2241 V(vsro, VSRO, 0x1000044C) \
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2426 __ vsro(tempFPReg1, src0, tempFPReg2); in AssembleArchInstruction() local
2427 __ vsro(tempFPReg2, src1, tempFPReg2); in AssembleArchInstruction() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td711 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td718 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4357 "vsr\005vsrab\005vsrad\005vsrah\005vsraw\004vsrb\004vsrd\004vsrh\004vsro"
6662 …{ 11946 /* vsro */, PPC::VSRO, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, MCK_…
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc4922 ppc_altivec_vsro, // llvm.ppc.altivec.vsro
DIntrinsicImpl.inc4948 "llvm.ppc.altivec.vsro",
13826 1, // llvm.ppc.altivec.vsro
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3978 ppc_altivec_vsro, // llvm.ppc.altivec.vsro
10002 "llvm.ppc.altivec.vsro",
17887 1, // llvm.ppc.altivec.vsro
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3984 ppc_altivec_vsro, // llvm.ppc.altivec.vsro
10042 "llvm.ppc.altivec.vsro",
17982 1, // llvm.ppc.altivec.vsro
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3984 ppc_altivec_vsro, // llvm.ppc.altivec.vsro
10042 "llvm.ppc.altivec.vsro",
17982 1, // llvm.ppc.altivec.vsro
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3984 ppc_altivec_vsro, // llvm.ppc.altivec.vsro
10042 "llvm.ppc.altivec.vsro",
17982 1, // llvm.ppc.altivec.vsro
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3984 ppc_altivec_vsro, // llvm.ppc.altivec.vsro
10042 "llvm.ppc.altivec.vsro",
17982 1, // llvm.ppc.altivec.vsro