Searched refs:vsubfp (Results 1 – 14 of 14) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | vec_fneg.ll | 18 ; CHECK-NOVSX: vsubfp
|
| D | vec_abs.ll | 47 ; CHECK-NOVSX: vsubfp
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vec_fneg.ll | 18 ; CHECK-NOVSX: vsubfp
|
| D | vec_abs.ll | 47 ; CHECK-NOVSX: vsubfp
|
| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s.cs | 144 0x10,0x43,0x20,0x4a = vsubfp 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 622 # CHECK-BE: vsubfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4a]
623 # CHECK-LE: vsubfp 2, 3, 4 # encoding: [0x4a,0x20,0x43,0x10]
624 vsubfp 2, 3, 4
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 616 # CHECK-BE: vsubfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4a]
617 # CHECK-LE: vsubfp 2, 3, 4 # encoding: [0x4a,0x20,0x43,0x10]
618 vsubfp 2, 3, 4
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 564 # CHECK: vsubfp 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 564 # CHECK: vsubfp 2, 3, 4
|
| /external/v8/src/codegen/ppc/ |
| D | constants-ppc.h | 2255 V(vsubfp, VSUBFP, 0x1000004A) \
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 644 "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 645 "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
|
| /external/v8/src/compiler/backend/ppc/ |
| D | code-generator-ppc.cc | 2434 __ vsubfp(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 6669 …{ 11995 /* vsubfp */, PPC::VSUBFP, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC, …
|