Searched refs:vsububs (Results 1 – 21 of 21) sorted by relevance
| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s.cs | 65 0x10,0x43,0x26,0x00 = vsububs 2, 3, 4
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 283 # CHECK-BE: vsububs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x00]
284 # CHECK-LE: vsububs 2, 3, 4 # encoding: [0x00,0x26,0x43,0x10]
285 vsububs 2, 3, 4
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| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-vmx.s | 283 # CHECK-BE: vsububs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x00]
284 # CHECK-LE: vsububs 2, 3, 4 # encoding: [0x00,0x26,0x43,0x10]
285 vsububs 2, 3, 4
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| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 252 # CHECK: vsububs 2, 3, 4
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-vmx.txt | 252 # CHECK: vsububs 2, 3, 4
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | xtype_alu.ll | 1004 declare i64 @llvm.hexagon.A2.vsububs(i64, i64)
1006 %z = call i64 @llvm.hexagon.A2.vsububs(i64 %a, i64 %b)
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| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | xtype_alu.ll | 1004 declare i64 @llvm.hexagon.A2.vsububs(i64, i64)
1006 %z = call i64 @llvm.hexagon.A2.vsububs(i64 %a, i64 %b)
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsPowerPC.td | 370 def int_ppc_altivec_vsububs : PowerPC_Vec_BBB_Intrinsic<"vsububs">;
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | IntrinsicsPowerPC.td | 444 def int_ppc_altivec_vsububs : PowerPC_Vec_BBB_Intrinsic<"vsububs">;
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| /external/v8/src/codegen/ppc/ |
| D | constants-ppc.h | 2361 V(vsububs, VSUBUBS, 0x10000600) \
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 659 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 660 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
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| /external/v8/src/compiler/backend/ppc/ |
| D | code-generator-ppc.cc | 3224 __ vsububs(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 4359 "p\007vsubsbs\007vsubshs\007vsubsws\007vsububm\007vsububs\007vsubudm\007"
6674 …{ 12034 /* vsububs */, PPC::VSUBUBS, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC…
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| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1390 hexagon_A2_vsububs, // llvm.hexagon.A2.vsububs
4932 ppc_altivec_vsububs, // llvm.ppc.altivec.vsububs
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| D | IntrinsicImpl.inc | 1416 "llvm.hexagon.A2.vsububs",
4958 "llvm.ppc.altivec.vsububs",
10294 1, // llvm.hexagon.A2.vsububs
13836 1, // llvm.ppc.altivec.vsububs
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| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 844 hexagon_A2_vsububs, // llvm.hexagon.A2.vsububs
3988 ppc_altivec_vsububs, // llvm.ppc.altivec.vsububs
6868 "llvm.hexagon.A2.vsububs",
10012 "llvm.ppc.altivec.vsububs",
14753 1, // llvm.hexagon.A2.vsububs
17897 1, // llvm.ppc.altivec.vsububs
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| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 850 hexagon_A2_vsububs, // llvm.hexagon.A2.vsububs
3994 ppc_altivec_vsububs, // llvm.ppc.altivec.vsububs
6908 "llvm.hexagon.A2.vsububs",
10052 "llvm.ppc.altivec.vsububs",
14848 1, // llvm.hexagon.A2.vsububs
17992 1, // llvm.ppc.altivec.vsububs
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| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 850 hexagon_A2_vsububs, // llvm.hexagon.A2.vsububs
3994 ppc_altivec_vsububs, // llvm.ppc.altivec.vsububs
6908 "llvm.hexagon.A2.vsububs",
10052 "llvm.ppc.altivec.vsububs",
14848 1, // llvm.hexagon.A2.vsububs
17992 1, // llvm.ppc.altivec.vsububs
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| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 850 hexagon_A2_vsububs, // llvm.hexagon.A2.vsububs
3994 ppc_altivec_vsububs, // llvm.ppc.altivec.vsububs
6908 "llvm.hexagon.A2.vsububs",
10052 "llvm.ppc.altivec.vsububs",
14848 1, // llvm.hexagon.A2.vsububs
17992 1, // llvm.ppc.altivec.vsububs
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| /external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/ |
| D | Intrinsics.gen | 850 hexagon_A2_vsububs, // llvm.hexagon.A2.vsububs
3994 ppc_altivec_vsububs, // llvm.ppc.altivec.vsububs
6908 "llvm.hexagon.A2.vsububs",
10052 "llvm.ppc.altivec.vsububs",
14848 1, // llvm.hexagon.A2.vsububs
17992 1, // llvm.ppc.altivec.vsububs
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