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Searched refs:vsubuhs (Results 1 – 21 of 21) sorted by relevance

/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs66 0x10,0x43,0x26,0x40 = vsubuhs 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s286 # CHECK-BE: vsubuhs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x40]
287 # CHECK-LE: vsubuhs 2, 3, 4 # encoding: [0x40,0x26,0x43,0x10]
288 vsubuhs 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s286 # CHECK-BE: vsubuhs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x40]
287 # CHECK-LE: vsubuhs 2, 3, 4 # encoding: [0x40,0x26,0x43,0x10]
288 vsubuhs 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt255 # CHECK: vsubuhs 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt255 # CHECK: vsubuhs 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll989 declare i64 @llvm.hexagon.A2.vsubuhs(i64, i64)
991 %z = call i64 @llvm.hexagon.A2.vsubuhs(i64 %a, i64 %b)
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll989 declare i64 @llvm.hexagon.A2.vsubuhs(i64, i64)
991 %z = call i64 @llvm.hexagon.A2.vsubuhs(i64 %a, i64 %b)
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td372 def int_ppc_altivec_vsubuhs : PowerPC_Vec_HHH_Intrinsic<"vsubuhs">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td446 def int_ppc_altivec_vsubuhs : PowerPC_Vec_HHH_Intrinsic<"vsubuhs">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2353 V(vsubuhs, VSUBUHS, 0x10000640) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td660 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td661 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc3204 __ vsubuhs(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4360 "vsubuhm\007vsubuhs\007vsubuqm\007vsubuwm\007vsubuws\010vsum2sws\010vsum"
6677 …{ 12058 /* vsubuhs */, PPC::VSUBUHS, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, 0, { MCK_RegVRRC…
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1391 hexagon_A2_vsubuhs, // llvm.hexagon.A2.vsubuhs
4933 ppc_altivec_vsubuhs, // llvm.ppc.altivec.vsubuhs
DIntrinsicImpl.inc1417 "llvm.hexagon.A2.vsubuhs",
4959 "llvm.ppc.altivec.vsubuhs",
10295 1, // llvm.hexagon.A2.vsubuhs
13837 1, // llvm.ppc.altivec.vsubuhs
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen845 hexagon_A2_vsubuhs, // llvm.hexagon.A2.vsubuhs
3989 ppc_altivec_vsubuhs, // llvm.ppc.altivec.vsubuhs
6869 "llvm.hexagon.A2.vsubuhs",
10013 "llvm.ppc.altivec.vsubuhs",
14754 1, // llvm.hexagon.A2.vsubuhs
17898 1, // llvm.ppc.altivec.vsubuhs
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen851 hexagon_A2_vsubuhs, // llvm.hexagon.A2.vsubuhs
3995 ppc_altivec_vsubuhs, // llvm.ppc.altivec.vsubuhs
6909 "llvm.hexagon.A2.vsubuhs",
10053 "llvm.ppc.altivec.vsubuhs",
14849 1, // llvm.hexagon.A2.vsubuhs
17993 1, // llvm.ppc.altivec.vsubuhs
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen851 hexagon_A2_vsubuhs, // llvm.hexagon.A2.vsubuhs
3995 ppc_altivec_vsubuhs, // llvm.ppc.altivec.vsubuhs
6909 "llvm.hexagon.A2.vsubuhs",
10053 "llvm.ppc.altivec.vsubuhs",
14849 1, // llvm.hexagon.A2.vsubuhs
17993 1, // llvm.ppc.altivec.vsubuhs
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen851 hexagon_A2_vsubuhs, // llvm.hexagon.A2.vsubuhs
3995 ppc_altivec_vsubuhs, // llvm.ppc.altivec.vsubuhs
6909 "llvm.hexagon.A2.vsubuhs",
10053 "llvm.ppc.altivec.vsubuhs",
14849 1, // llvm.hexagon.A2.vsubuhs
17993 1, // llvm.ppc.altivec.vsubuhs
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen851 hexagon_A2_vsubuhs, // llvm.hexagon.A2.vsubuhs
3995 ppc_altivec_vsubuhs, // llvm.ppc.altivec.vsubuhs
6909 "llvm.hexagon.A2.vsubuhs",
10053 "llvm.ppc.altivec.vsubuhs",
14849 1, // llvm.hexagon.A2.vsubuhs
17993 1, // llvm.ppc.altivec.vsubuhs