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Searched refs:vupklsb (Results 1 – 19 of 19) sorted by relevance

/external/llvm/test/CodeGen/PowerPC/
Dvsx-spill-norwstore.ll16 …%1 = tail call <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0…
53 declare <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8>) #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvsx-spill-norwstore.ll18 …%1 = tail call <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0…
55 declare <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8>) #1
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-vmx.s.cs27 0x10,0x40,0x1a,0x8e = vupklsb 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s88 # CHECK-BE: vupklsb 2, 3 # encoding: [0x10,0x40,0x1a,0x8e]
89 # CHECK-LE: vupklsb 2, 3 # encoding: [0x8e,0x1a,0x40,0x10]
90 vupklsb 2, 3
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s88 # CHECK-BE: vupklsb 2, 3 # encoding: [0x10,0x40,0x1a,0x8e]
89 # CHECK-LE: vupklsb 2, 3 # encoding: [0x8e,0x1a,0x40,0x10]
90 vupklsb 2, 3
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt78 # CHECK: vupklsb 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt78 # CHECK: vupklsb 2, 3
/external/v8/src/codegen/ppc/
Dconstants-ppc.h2381 V(vupklsb, VUPKLSB, 0x1000028E) \
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc3122 __ vupklsb(i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction() local
3130 __ vupklsb(i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td764 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td771 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4362 "h\007vupkhsw\007vupklpx\007vupklsb\007vupklsh\007vupklsw\004vxor\004wai"
6691 …{ 12174 /* vupklsb */, PPC::VUPKLSB, Convert__RegVRRC1_0__RegVRRC1_1, 0, { MCK_RegVRRC, MCK_RegVRR…
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc4945 ppc_altivec_vupklsb, // llvm.ppc.altivec.vupklsb
DIntrinsicImpl.inc4971 "llvm.ppc.altivec.vupklsb",
13849 1, // llvm.ppc.altivec.vupklsb
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen4001 ppc_altivec_vupklsb, // llvm.ppc.altivec.vupklsb
10025 "llvm.ppc.altivec.vupklsb",
17910 1, // llvm.ppc.altivec.vupklsb
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen4007 ppc_altivec_vupklsb, // llvm.ppc.altivec.vupklsb
10065 "llvm.ppc.altivec.vupklsb",
18005 1, // llvm.ppc.altivec.vupklsb
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen4007 ppc_altivec_vupklsb, // llvm.ppc.altivec.vupklsb
10065 "llvm.ppc.altivec.vupklsb",
18005 1, // llvm.ppc.altivec.vupklsb
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen4007 ppc_altivec_vupklsb, // llvm.ppc.altivec.vupklsb
10065 "llvm.ppc.altivec.vupklsb",
18005 1, // llvm.ppc.altivec.vupklsb
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen4007 ppc_altivec_vupklsb, // llvm.ppc.altivec.vupklsb
10065 "llvm.ppc.altivec.vupklsb",
18005 1, // llvm.ppc.altivec.vupklsb