| /external/libgav1/libgav1/src/ |
| D | quantizer_tables.inc | 32 // Size 4x4
135 // Size 8x4
237 // Size 16x4
281 // Size 4x4
371 // Size 8x4
461 // Size 16x4
504 // Size 4x4
604 // Size 8x4
704 // Size 16x4
747 // Size 4x4
[all …]
|
| /external/libavc/common/armv8/ |
| D | ih264_padding_neon_av8.s | 98 mov x4, x5
103 st1 {v0.8b, v1.8b}, [x4], x6
180 sub x4, x0, x3
192 st1 {v0.16b}, [x4], x1 // 16 bytes store
194 st1 {v2.16b}, [x4], x1 // 16 bytes store
199 st1 {v4.16b}, [x4], x1 // 16 bytes store
202 st1 {v6.16b}, [x4], x1 // 16 bytes store
208 st1 {v0.16b}, [x4], x1 // 16 bytes store
212 st1 {v2.16b}, [x4], x1 // 16 bytes store
216 st1 {v4.16b}, [x4], x1 // 16 bytes store
[all …]
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| D | ih264_default_weighted_pred_av8.s | 117 sxtw x4, w4
128 ld1 {v2.s}[0], [x1], x4 //load row 1 in source 2
129 ld1 {v2.s}[1], [x1], x4 //load row 2 in source 2
133 ld1 {v3.s}[0], [x1], x4 //load row 3 in source 2
134 ld1 {v3.s}[1], [x1], x4 //load row 4 in source 2
147 ld1 {v4.8b}, [x1], x4 //load row 1 in source 2
149 ld1 {v5.8b}, [x1], x4 //load row 2 in source 2
153 ld1 {v6.8b}, [x1], x4 //load row 3 in source 2
156 ld1 {v7.8b}, [x1], x4 //load row 4 in source 2
169 ld1 {v16.8b, v17.8b}, [x1], x4 //load row 1 in source 2
[all …]
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| D | ih264_iquant_itrans_recon_dc_av8.s | 123 sxtw x4, w4
164 st1 {v1.s}[0], [x2], x4
165 st1 {v1.s}[1], [x2], x4
166 st1 {v2.s}[0], [x2], x4
229 sxtw x4, w4
248 ld1 {v11.d}[0], [x2], x4 //load pu1_out for interleaving
249 ld1 {v11.d}[1], [x2], x4
250 ld1 {v12.d}[0], [x2], x4
268 st1 {v11.d}[0], [x0], x4
269 st1 {v11.d}[1], [x0], x4
[all …]
|
| /external/libaom/libaom/av1/encoder/x86/ |
| D | av1_fwd_txfm_sse2.c | 132 __m128i x4[8]; in fdct4x8_new_sse2() local
133 x4[0] = x3[0]; in fdct4x8_new_sse2()
134 x4[1] = x3[1]; in fdct4x8_new_sse2()
135 x4[2] = x3[2]; in fdct4x8_new_sse2()
136 x4[3] = x3[3]; in fdct4x8_new_sse2()
138 &x3[7], &x4[4], &x4[7]); in fdct4x8_new_sse2()
140 &x3[6], &x4[5], &x4[6]); in fdct4x8_new_sse2()
143 output[0] = x4[0]; in fdct4x8_new_sse2()
144 output[1] = x4[4]; in fdct4x8_new_sse2()
145 output[2] = x4[2]; in fdct4x8_new_sse2()
[all …]
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| D | av1_fwd_txfm1d_sse4.c | 812 __m128i x4[64]; in av1_fdct64_sse4_1() local
813 x4[0] = _mm_add_epi32(x3[0], x3[7]); in av1_fdct64_sse4_1()
814 x4[7] = _mm_sub_epi32(x3[0], x3[7]); in av1_fdct64_sse4_1()
815 x4[1] = _mm_add_epi32(x3[1], x3[6]); in av1_fdct64_sse4_1()
816 x4[6] = _mm_sub_epi32(x3[1], x3[6]); in av1_fdct64_sse4_1()
817 x4[2] = _mm_add_epi32(x3[2], x3[5]); in av1_fdct64_sse4_1()
818 x4[5] = _mm_sub_epi32(x3[2], x3[5]); in av1_fdct64_sse4_1()
819 x4[3] = _mm_add_epi32(x3[3], x3[4]); in av1_fdct64_sse4_1()
820 x4[4] = _mm_sub_epi32(x3[3], x3[4]); in av1_fdct64_sse4_1()
821 x4[8] = x3[8]; in av1_fdct64_sse4_1()
[all …]
|
| /external/arm-trusted-firmware/plat/arm/board/n1sdp/aarch64/ |
| D | n1sdp_helper.S | 33 mov x4, x0
41 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
47 mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP
48 madd x2, x3, x4, x2
49 mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
50 madd x1, x2, x4, x1
51 mov x4, #N1SDP_MAX_PE_PER_CPU
[all …]
|
| /external/boringssl/ios-aarch64/crypto/third_party/sike/asm/ |
| D | fp-armv8.S | 41 ldp x3, x4, [x0]
52 adcs x4, x4, x8
78 and x21, x4, x8
90 stp x3, x4, [x2,#0]
93 adcs x4, x4, x6
109 and x22, x4, x20
122 mul x3, x4, x23
123 umulh x23, x4, x23
127 mul x24, x4, x26
128 umulh x26, x4, x26
[all …]
|
| /external/libhevc/common/arm64/ |
| D | ihevc_padding.s | 99 sub x4,x0,x3
115 add x5,x4,x1
117 st1 {v0.16b},[x4],#16 //128/8 = 16 bytes store
118 st1 {v0.16b},[x4],#16 // 16 bytes store
119 st1 {v0.16b},[x4],#16 // 16 bytes store
120 st1 {v0.16b},[x4],#16 // 16 bytes store
121 st1 {v0.16b},[x4] // 16 bytes store
217 sub x4,x0,x3
233 add x5,x4,x1
235 st1 {v0.16b},[x4],#16 //128/8 = 16 bytes store
[all …]
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| D | ihevc_inter_pred_filters_luma_horz.s | 123 mov x15,x4 // pi1_coeff
131 mov x4,x15 //loads pi1_coeff
135 ld1 {v0.8b},[x4] //coeff = vld1_s8(pi1_coeff)
147 add x4,x12,x2 //pu1_src_tmp2_8 = pu1_src + src_strd
198 add x4,x12,x2 //pu1_src + src_strd
236 ld1 {v12.2s},[x4],x11 //vector load pu1_src + src_strd
238 ld1 {v13.2s},[x4],x11
240 ld1 {v14.2s},[x4],x11
242 ld1 {v15.2s},[x4],x11
244 ld1 {v16.2s},[x4],x11 //vector load pu1_src + src_strd
[all …]
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| D | ihevc_inter_pred_chroma_horz_w16out.s | 113 mov x15,x4 // pi1_coeff
117 mov x4,x15 //loads pi1_coeff
121 ld1 {v0.8b},[x4] //coeff = vld1_s8(pi1_coeff)
134 add x4,x12,x2 //pu1_src_tmp2_8 = pu1_src + src_strd
174 add x4,x12,x2
193 add x20,x4, x2 , lsl #1
205 add x19,x4,#8
207 ld1 { v29.2s},[x4],x11 //vector load pu1_src
212 ld1 { v10.2s},[x4],x11 //vector load pu1_src
217 ld1 { v12.2s},[x4],x11 //vector load pu1_src
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/ |
| D | selects.ll | 30 %base.x4 = shl i32 %base, 2
31 %base.x4.p1 = add i32 %base.x4, 1
32 %base.x4.p2 = add i32 %base.x4, 2
33 %base.x4.p3 = add i32 %base.x4, 3
34 %zext.x4 = zext i32 %base.x4 to i64
35 %zext.x4.p1 = zext i32 %base.x4.p1 to i64
36 %zext.x4.p2 = zext i32 %base.x4.p2 to i64
37 %zext.x4.p3 = zext i32 %base.x4.p3 to i64
38 %base.x16 = mul i64 %zext.x4, 4
39 %base.x16.p4 = shl i64 %zext.x4.p1, 2
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-memory.s | 8 ldr w5, [x4, #20]
9 ldr x4, [x3]
17 ldrb w5, [x4, #20]
41 prfm pstl3strm, [x4, x5, lsl #3]
43 ; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9]
44 ; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9]
52 ; CHECK: ldrb w5, [x4, #20] ; encoding: [0x85,0x50,0x40,0x39]
75 ; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8]
81 str x4, [x3]
83 str w5, [x4, #20]
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-memory.s | 8 ldr w5, [x4, #20]
9 ldr x4, [x3]
17 ldrb w5, [x4, #20]
41 prfm pstl3strm, [x4, x5, lsl #3]
43 ; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9]
44 ; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9]
52 ; CHECK: ldrb w5, [x4, #20] ; encoding: [0x85,0x50,0x40,0x39]
75 ; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8]
81 str x4, [x3]
83 str w5, [x4, #20]
[all …]
|
| /external/mesa3d/src/amd/addrlib/src/r800/ |
| D | siaddrlib.cpp | 231 ADDR_CHANNEL_SETTING x4 = InitChannel(1, 0, log2BytesPP + bankXStart + 1); in ComputeBankEquation() local
240 x4.value = (threshX > bankXStart + 1) ? x4.value : 0; in ComputeBankEquation()
257 pEquation->xor2[1] = x4; in ComputeBankEquation()
269 pEquation->xor2[1] = x4; in ComputeBankEquation()
279 pEquation->addr[1] = x4; in ComputeBankEquation()
291 pEquation->addr[1] = x4; in ComputeBankEquation()
312 pEquation->xor2[1] = x4; in ComputeBankEquation()
322 pEquation->xor2[1] = x4; in ComputeBankEquation()
330 pEquation->addr[1] = x4; in ComputeBankEquation()
348 pEquation->xor1[1] = x4; in ComputeBankEquation()
[all …]
|
| /external/arm-trusted-firmware/common/aarch64/ |
| D | debug.S | 41 udiv x0, x4, x5 /* Get the quotient */
42 msub x4, x0, x5, x4 /* Find the remainder */
72 adr x4, assert_msg1
74 mov x4, x5
76 adr x4, assert_msg2
81 mov x4, x6
98 ldrb w0, [x4], #0x1
119 lsrv x0, x4, x5
181 adr x4, panic_msg
183 mov x4, x6
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/ |
| D | binaryFloatInstructions.3.2.ll | 8 define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
19 ; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4
20 %res4 = fadd fp128 %x4, %x4
31 define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x…
42 ; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4
43 %res4 = fadd <8 x float> %x4, %x4
51 define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, …
62 ; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4
63 %res4 = fadd <8 x double> %x4, %x4
71 define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half…
[all …]
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| D | binaryIntInstructions.3.2.ll | 8 define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
19 ; CHECK-NEXT: %res4 = add i32 %x4, %x4
20 %res4 = add i32 %x4, %x4
37 define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
48 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4
49 %res4 = add nuw nsw <8 x i8> %x4, %x4
57 define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> …
68 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4
69 %res4 = add nuw nsw <8 x i16> %x4, %x4
77 define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> …
[all …]
|
| /external/llvm/test/Bitcode/ |
| D | binaryFloatInstructions.3.2.ll | 8 define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
19 ; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4
20 %res4 = fadd fp128 %x4, %x4
31 define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x…
42 ; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4
43 %res4 = fadd <8 x float> %x4, %x4
51 define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, …
62 ; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4
63 %res4 = fadd <8 x double> %x4, %x4
71 define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half…
[all …]
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| D | binaryIntInstructions.3.2.ll | 8 define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
19 ; CHECK-NEXT: %res4 = add i32 %x4, %x4
20 %res4 = add i32 %x4, %x4
37 define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
48 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4
49 %res4 = add nuw nsw <8 x i8> %x4, %x4
57 define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> …
68 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4
69 %res4 = add nuw nsw <8 x i16> %x4, %x4
77 define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> …
[all …]
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| /external/libmpeg2/common/armv8/ |
| D | impeg2_inter_pred.s | 109 ldr x4, [x0] //src->y
113 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
117 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
119 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
121 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
123 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
125 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
127 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
129 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
131 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
[all …]
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| /external/pdfium/third_party/agg23/ |
| D | agg_curves.cpp | 32 float x4, float y4) in init() argument
37 bezier(x1, y1, x2, y2, x3, y3, x4, y4); in init()
43 float x4, float y4, in recursive_bezier() argument
53 float x34 = (x3 + x4) / 2; in recursive_bezier()
61 float dx = x4 - x1; in recursive_bezier()
63 float d2 = fabs(((x2 - x4) * dy) - ((y2 - y4) * dx)); in recursive_bezier()
64 float d3 = fabs(((x3 - x4) * dy) - ((y3 - y4) * dx)); in recursive_bezier()
69 fabs(x2 + x4 - x3 - x3) + fabs(y2 + y4 - y3 - y3) <= in recursive_bezier()
98 recursive_bezier(x1234, y1234, x234, y234, x34, y34, x4, y4, level + 1); in recursive_bezier()
103 float x4, float y4) in bezier() argument
[all …]
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| D | agg_curves.h | 28 float x4, float y4) in curve4_points()
36 cp[6] = x4; in curve4_points()
42 float x4, float y4) in init()
50 cp[6] = x4; in init()
71 float x4, float y4) : in curve4_div() argument
74 init(x1, y1, x2, y2, x3, y3, x4, y4); in curve4_div()
89 float x4, float y4);
127 float x4, float y4);
131 float x4, float y4,
145 float x4, float y4) in curve4() argument
[all …]
|
| /external/XNNPACK/src/f32-gemm/gen-inc/ |
| D | 4x8-aarch64-neonfma-cortex-a53.S | 17 # size_t a_stride, x4
40 # x4 temporary vector shadow register
69 ADD x9, x3, x4 // a1 = a0 + a_stride
74 ADD x10, x9, x4 // a2 = a1 + a_stride
81 ADD x11, x10, x4 // a3 = a2 + a_stride
131 LDR x4, [x5], 8 // ins is in BLOCK 0
142 INS v19.d[1], x4 // b from second group
144 LDR x4, [x9], 8 // a1
150 INS v3.d[1], x4 // a1 ins
152 LDR x4, [x5, 8] // b
[all …]
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| /external/XNNPACK/src/f32-gemm/gen/ |
| D | 4x8-aarch64-neonfma-cortex-a53.S | 17 # size_t a_stride, x4
39 # x4 temporary vector shadow register
68 ADD x9, x3, x4 // a1 = a0 + a_stride
73 ADD x10, x9, x4 // a2 = a1 + a_stride
80 ADD x11, x10, x4 // a3 = a2 + a_stride
133 LDR x4, [x5], 8 // ins is in BLOCK 0
144 INS v19.d[1], x4 // b from second group
146 LDR x4, [x9], 8 // a1
152 INS v3.d[1], x4 // a1 ins
154 LDR x4, [x5, 8] // b
[all …]
|