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Searched refs:xreg (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/arch/arm/include/asm/
Dmacro.h70 .macro switch_el, xreg, el3_label, el2_label, el1_label
71 mrs \xreg, CurrentEL
72 cmp \xreg, 0xc
74 cmp \xreg, 0x8
76 cmp \xreg, 0x4
83 .macro branch_if_a57_core, xreg, a57_label
84 mrs \xreg, midr_el1
85 lsr \xreg, \xreg, #4
86 and \xreg, \xreg, #0x00000FFF
87 cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
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/external/vixl/test/aarch64/examples/
Dtest-examples.cc199 VIXL_CHECK(static_cast<uint64_t>(regs.xreg(0)) == FactorialC(N)); \
224 VIXL_CHECK(static_cast<uint64_t>(regs.xreg(0)) == FactorialC(N)); \
407 VIXL_CHECK(regs.xreg(0) == SumArrayC(Array, ARRAY_SIZE(Array))); \
435 VIXL_CHECK(regs.xreg(0) == abs(X)); \
468 VIXL_CHECK(regs.xreg(0) == chksum); in TEST()
490 VIXL_CHECK(regs.xreg(0) == d); in TEST()
491 VIXL_CHECK(regs.xreg(1) == c); in TEST()
492 VIXL_CHECK(regs.xreg(2) == b); in TEST()
493 VIXL_CHECK(regs.xreg(3) == a); in TEST()
522 VIXL_CHECK(regs.xreg(0) == ((Low <= Value) && (Value <= High))); \
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/external/vixl/test/aarch64/
Dtest-utils-aarch64.cc176 int64_t result_x = core->xreg(reg.GetCode()); in Equal32()
193 uint64_t result = core->xreg(reg.GetCode()); in Equal64()
202 uint64_t result = core->xreg(reg.GetCode()); in NotEqual64()
268 int64_t reference = core->xreg(reg0.GetCode()); in Equal64()
269 int64_t result = core->xreg(reg1.GetCode()); in Equal64()
278 int64_t expected = core->xreg(reg0.GetCode()); in NotEqual64()
279 int64_t result = core->xreg(reg1.GetCode()); in NotEqual64()
327 if (a->xreg(i) != b->xreg(i)) { in EqualRegisters()
330 a->xreg(i), in EqualRegisters()
331 b->xreg(i)); in EqualRegisters()
Dtest-utils-aarch64.h94 inline int64_t xreg(unsigned code) const { in xreg() function
/external/v8/src/execution/arm64/
Dsimulator-arm64.cc191 saved_registers[i] = xreg(PopLowestIndexAsCode(&register_list)); in CheckPCSComplianceAndRun()
208 DCHECK_EQ(saved_registers[i], xreg(PopLowestIndexAsCode(&register_list))); in CheckPCSComplianceAndRun()
498 const int64_t arg0 = xreg(0); in DoRuntimeCall()
499 const int64_t arg1 = xreg(1); in DoRuntimeCall()
500 const int64_t arg2 = xreg(2); in DoRuntimeCall()
501 const int64_t arg3 = xreg(3); in DoRuntimeCall()
502 const int64_t arg4 = xreg(4); in DoRuntimeCall()
503 const int64_t arg5 = xreg(5); in DoRuntimeCall()
504 const int64_t arg6 = xreg(6); in DoRuntimeCall()
505 const int64_t arg7 = xreg(7); in DoRuntimeCall()
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Dsimulator-arm64.h926 int64_t xreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
1008 int64_t sp() { return xreg(31, Reg31IsStackPointer); } in sp()
1009 int64_t fp() { return xreg(kFramePointerRegCode, Reg31IsStackPointer); } in fp()
2444 return ConvertReturn<T>(xreg(0)); in ReadReturn()
/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dlowlevel.S247 .macro tzasc_prog, xreg argument
251 mul x14, \xreg, x16
/external/vixl/src/aarch64/
Dsimulator-aarch64.h825 int64_t xreg(unsigned code,