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Searched refs:xvcmpeqsp (Results 1 – 22 of 22) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvsx.ll412 ; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37
417 ; CHECK-FISL: xvcmpeqsp [[V1:[0-9]+]], 36, 37
422 ; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37
434 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
435 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
436 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
445 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
446 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
447 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
456 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
[all …]
Dbuiltins-ppc-elf2-abi.ll82 %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %0, <4 x float> %1)
86 ; CHECK: xvcmpeqsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
257 declare <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float>, <4 x float>)
/external/llvm/test/CodeGen/PowerPC/
Dvsx.ll460 ; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37
469 ; CHECK-FISL: xvcmpeqsp 32, 33, 32
475 ; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37
487 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
488 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
489 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
498 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 32
499 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 32, 32
500 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 33
509 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
[all …]
Dbuiltins-ppc-elf2-abi.ll82 %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %0, <4 x float> %1)
86 ; CHECK: xvcmpeqsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
183 declare <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float>, <4 x float>)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dvsx.s233 # CHECK-BE: xvcmpeqsp 7, 63, 27 # encoding: [0xf0,0xff,0xda,0x1c]
234 # CHECK-LE: xvcmpeqsp 7, 63, 27 # encoding: [0x1c,0xda,0xff,0xf0]
235 xvcmpeqsp 7, 63, 27
236 # CHECK-BE: xvcmpeqsp. 7, 63, 27 # encoding: [0xf0,0xff,0xde,0x1c]
237 # CHECK-LE: xvcmpeqsp. 7, 63, 27 # encoding: [0x1c,0xde,0xff,0xf0]
238 xvcmpeqsp. 7, 63, 27
/external/llvm/test/MC/PowerPC/
Dvsx.s233 # CHECK-BE: xvcmpeqsp 7, 63, 27 # encoding: [0xf0,0xff,0xda,0x1c]
234 # CHECK-LE: xvcmpeqsp 7, 63, 27 # encoding: [0x1c,0xda,0xff,0xf0]
235 xvcmpeqsp 7, 63, 27
236 # CHECK-BE: xvcmpeqsp. 7, 63, 27 # encoding: [0xf0,0xff,0xde,0x1c]
237 # CHECK-LE: xvcmpeqsp. 7, 63, 27 # encoding: [0x1c,0xde,0xff,0xf0]
238 xvcmpeqsp. 7, 63, 27
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt228 # CHECK: xvcmpeqsp 7, 63, 27
231 # CHECK: xvcmpeqsp. 7, 63, 27
/external/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt228 # CHECK: xvcmpeqsp 7, 63, 27
231 # CHECK: xvcmpeqsp. 7, 63, 27
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td717 PowerPC_VSX_Intrinsic<"xvcmpeqsp", [llvm_v4i32_ty],
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2645 __ xvcmpeqsp(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
2670 __ xvcmpeqsp(kScratchDoubleReg, i.InputSimd128Register(0), in AssembleArchInstruction() local
3075 __ xvcmpeqsp(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); in AssembleArchInstruction() local
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td833 PowerPC_VSX_Intrinsic<"xvcmpeqsp", [llvm_v4i32_ty],
/external/v8/src/codegen/ppc/
Dconstants-ppc.h212 V(xvcmpeqsp, XVCMPEQSP, 0xF0000218) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td470 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc6826 …{ 13360 /* xvcmpeqsp */, PPC::XVCMPEQSP, Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2, 0, { MCK_Reg…
6827 …{ 13360 /* xvcmpeqsp */, PPC::XVCMPEQSPo, Convert__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3, 0, { MCK__D…
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc5094 ppc_vsx_xvcmpeqsp, // llvm.ppc.vsx.xvcmpeqsp
5095 ppc_vsx_xvcmpeqsp_p, // llvm.ppc.vsx.xvcmpeqsp.p
DIntrinsicImpl.inc5120 "llvm.ppc.vsx.xvcmpeqsp",
5121 "llvm.ppc.vsx.xvcmpeqsp.p",
13998 1, // llvm.ppc.vsx.xvcmpeqsp
13999 1, // llvm.ppc.vsx.xvcmpeqsp.p
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td514 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare,
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen4143 ppc_vsx_xvcmpeqsp, // llvm.ppc.vsx.xvcmpeqsp
4144 ppc_vsx_xvcmpeqsp_p, // llvm.ppc.vsx.xvcmpeqsp.p
10167 "llvm.ppc.vsx.xvcmpeqsp",
10168 "llvm.ppc.vsx.xvcmpeqsp.p",
18052 1, // llvm.ppc.vsx.xvcmpeqsp
18053 1, // llvm.ppc.vsx.xvcmpeqsp.p
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen4149 ppc_vsx_xvcmpeqsp, // llvm.ppc.vsx.xvcmpeqsp
4150 ppc_vsx_xvcmpeqsp_p, // llvm.ppc.vsx.xvcmpeqsp.p
10207 "llvm.ppc.vsx.xvcmpeqsp",
10208 "llvm.ppc.vsx.xvcmpeqsp.p",
18147 1, // llvm.ppc.vsx.xvcmpeqsp
18148 1, // llvm.ppc.vsx.xvcmpeqsp.p
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen4149 ppc_vsx_xvcmpeqsp, // llvm.ppc.vsx.xvcmpeqsp
4150 ppc_vsx_xvcmpeqsp_p, // llvm.ppc.vsx.xvcmpeqsp.p
10207 "llvm.ppc.vsx.xvcmpeqsp",
10208 "llvm.ppc.vsx.xvcmpeqsp.p",
18147 1, // llvm.ppc.vsx.xvcmpeqsp
18148 1, // llvm.ppc.vsx.xvcmpeqsp.p
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen4149 ppc_vsx_xvcmpeqsp, // llvm.ppc.vsx.xvcmpeqsp
4150 ppc_vsx_xvcmpeqsp_p, // llvm.ppc.vsx.xvcmpeqsp.p
10207 "llvm.ppc.vsx.xvcmpeqsp",
10208 "llvm.ppc.vsx.xvcmpeqsp.p",
18147 1, // llvm.ppc.vsx.xvcmpeqsp
18148 1, // llvm.ppc.vsx.xvcmpeqsp.p
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen4149 ppc_vsx_xvcmpeqsp, // llvm.ppc.vsx.xvcmpeqsp
4150 ppc_vsx_xvcmpeqsp_p, // llvm.ppc.vsx.xvcmpeqsp.p
10207 "llvm.ppc.vsx.xvcmpeqsp",
10208 "llvm.ppc.vsx.xvcmpeqsp.p",
18147 1, // llvm.ppc.vsx.xvcmpeqsp
18148 1, // llvm.ppc.vsx.xvcmpeqsp.p