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Searched refs:xvdivdp (Results 1 – 22 of 22) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvsx-div.ll21 %1 = tail call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %0)
26 ; CHECK: xvdivdp
28 declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)
Dbuiltins-ppc-elf2-abi.ll22 %2 = call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %1)
26 ; CHECK: xvdivdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
248 declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)
/external/llvm/test/CodeGen/PowerPC/
Dvsx-div.ll21 %1 = tail call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %0)
26 ; CHECK: xvdivdp
28 declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)
Dbuiltins-ppc-elf2-abi.ll22 %2 = call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %1)
26 ; CHECK: xvdivdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
174 declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dvsx.s323 # CHECK-BE: xvdivdp 7, 63, 27 # encoding: [0xf0,0xff,0xdb,0xc4]
324 # CHECK-LE: xvdivdp 7, 63, 27 # encoding: [0xc4,0xdb,0xff,0xf0]
325 xvdivdp 7, 63, 27
/external/llvm/test/MC/PowerPC/
Dvsx.s323 # CHECK-BE: xvdivdp 7, 63, 27 # encoding: [0xf0,0xff,0xdb,0xc4]
324 # CHECK-LE: xvdivdp 7, 63, 27 # encoding: [0xc4,0xdb,0xff,0xf0]
325 xvdivdp 7, 63, 27
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt318 # CHECK: xvdivdp 7, 63, 27
/external/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt318 # CHECK: xvdivdp 7, 63, 27
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td688 def int_ppc_vsx_xvdivdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvdivdp">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td804 def int_ppc_vsx_xvdivdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvdivdp">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h238 V(xvdivdp, XVDIVDP, 0xF00003C0) \
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc3309 __ xvdivdp(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td410 "xvdivdp $XT, $XA, $XB", IIC_FPDivD,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4387 "xdsp\txvcvuxwdp\txvcvuxwsp\007xvdivdp\007xvdivsp\010xviexpdp\010xviexps"
6858 …{ 13634 /* xvdivdp */, PPC::XVDIVDP, Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2, 0, { MCK_RegVSRC…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td454 "xvdivdp $XT, $XA, $XB", IIC_FPDivD,
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc5114 ppc_vsx_xvdivdp, // llvm.ppc.vsx.xvdivdp
DIntrinsicImpl.inc5140 "llvm.ppc.vsx.xvdivdp",
14018 1, // llvm.ppc.vsx.xvdivdp
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen4163 ppc_vsx_xvdivdp, // llvm.ppc.vsx.xvdivdp
10187 "llvm.ppc.vsx.xvdivdp",
18072 1, // llvm.ppc.vsx.xvdivdp
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen4169 ppc_vsx_xvdivdp, // llvm.ppc.vsx.xvdivdp
10227 "llvm.ppc.vsx.xvdivdp",
18167 1, // llvm.ppc.vsx.xvdivdp
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen4169 ppc_vsx_xvdivdp, // llvm.ppc.vsx.xvdivdp
10227 "llvm.ppc.vsx.xvdivdp",
18167 1, // llvm.ppc.vsx.xvdivdp
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen4169 ppc_vsx_xvdivdp, // llvm.ppc.vsx.xvdivdp
10227 "llvm.ppc.vsx.xvdivdp",
18167 1, // llvm.ppc.vsx.xvdivdp
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen4169 ppc_vsx_xvdivdp, // llvm.ppc.vsx.xvdivdp
10227 "llvm.ppc.vsx.xvdivdp",
18167 1, // llvm.ppc.vsx.xvdivdp