Home
last modified time | relevance | path

Searched refs:xvdivsp (Results 1 – 22 of 22) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvsx-div.ll11 %1 = tail call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %0)
16 ; CHECK: xvdivsp
29 declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)
Dbuiltins-ppc-elf2-abi.ll34 %2 = call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %1)
38 ; CHECK: xvdivsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
251 declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)
/external/llvm/test/CodeGen/PowerPC/
Dvsx-div.ll11 %1 = tail call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %0)
16 ; CHECK: xvdivsp
29 declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)
Dbuiltins-ppc-elf2-abi.ll34 %2 = call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %1)
38 ; CHECK: xvdivsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
177 declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dvsx.s326 # CHECK-BE: xvdivsp 7, 63, 27 # encoding: [0xf0,0xff,0xda,0xc4]
327 # CHECK-LE: xvdivsp 7, 63, 27 # encoding: [0xc4,0xda,0xff,0xf0]
328 xvdivsp 7, 63, 27
/external/llvm/test/MC/PowerPC/
Dvsx.s326 # CHECK-BE: xvdivsp 7, 63, 27 # encoding: [0xf0,0xff,0xda,0xc4]
327 # CHECK-LE: xvdivsp 7, 63, 27 # encoding: [0xc4,0xda,0xff,0xf0]
328 xvdivsp 7, 63, 27
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt321 # CHECK: xvdivsp 7, 63, 27
/external/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt321 # CHECK: xvdivsp 7, 63, 27
/external/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td689 def int_ppc_vsx_xvdivsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvdivsp">;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsPowerPC.td805 def int_ppc_vsx_xvdivsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvdivsp">;
/external/v8/src/codegen/ppc/
Dconstants-ppc.h240 V(xvdivsp, XVDIVSP, 0xF00002C0) \
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc3338 __ xvdivsp(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td414 "xvdivsp $XT, $XA, $XB", IIC_FPDivS,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4387 "xdsp\txvcvuxwdp\txvcvuxwsp\007xvdivdp\007xvdivsp\010xviexpdp\010xviexps"
6859 …{ 13642 /* xvdivsp */, PPC::XVDIVSP, Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2, 0, { MCK_RegVSRC…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td458 "xvdivsp $XT, $XA, $XB", IIC_FPDivS,
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc5115 ppc_vsx_xvdivsp, // llvm.ppc.vsx.xvdivsp
DIntrinsicImpl.inc5141 "llvm.ppc.vsx.xvdivsp",
14019 1, // llvm.ppc.vsx.xvdivsp
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen4164 ppc_vsx_xvdivsp, // llvm.ppc.vsx.xvdivsp
10188 "llvm.ppc.vsx.xvdivsp",
18073 1, // llvm.ppc.vsx.xvdivsp
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen4170 ppc_vsx_xvdivsp, // llvm.ppc.vsx.xvdivsp
10228 "llvm.ppc.vsx.xvdivsp",
18168 1, // llvm.ppc.vsx.xvdivsp
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen4170 ppc_vsx_xvdivsp, // llvm.ppc.vsx.xvdivsp
10228 "llvm.ppc.vsx.xvdivsp",
18168 1, // llvm.ppc.vsx.xvdivsp
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen4170 ppc_vsx_xvdivsp, // llvm.ppc.vsx.xvdivsp
10228 "llvm.ppc.vsx.xvdivsp",
18168 1, // llvm.ppc.vsx.xvdivsp
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen4170 ppc_vsx_xvdivsp, // llvm.ppc.vsx.xvdivsp
10228 "llvm.ppc.vsx.xvdivsp",
18168 1, // llvm.ppc.vsx.xvdivsp