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Searched refs:xvnegdp (Results 1 – 11 of 11) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvec_fneg.ll31 ; CHECK: xvnegdp
/external/llvm/test/CodeGen/PowerPC/
Dvec_fneg.ll31 ; CHECK: xvnegdp
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dvsx.s383 # CHECK-BE: xvnegdp 7, 27 # encoding: [0xf0,0xe0,0xdf,0xe4]
384 # CHECK-LE: xvnegdp 7, 27 # encoding: [0xe4,0xdf,0xe0,0xf0]
385 xvnegdp 7, 27
/external/llvm/test/MC/PowerPC/
Dvsx.s383 # CHECK-BE: xvnegdp 7, 27 # encoding: [0xf0,0xe0,0xdf,0xe4]
384 # CHECK-LE: xvnegdp 7, 27 # encoding: [0xe4,0xdf,0xe0,0xf0]
385 xvnegdp 7, 27
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt378 # CHECK: xvnegdp 7, 27
/external/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt378 # CHECK: xvnegdp 7, 27
/external/v8/src/codegen/ppc/
Dconstants-ppc.h366 V(xvnegdp, XVNEGDP, 0xF00007E4) \
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2921 __ xvnegdp(i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td533 "xvnegdp $XT, $XB", IIC_VecFP,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4390 "dp\txvmsubmsp\007xvmuldp\007xvmulsp\010xvnabsdp\010xvnabssp\007xvnegdp\007"
6880 …{ 13830 /* xvnegdp */, PPC::XVNEGDP, Convert__RegVSRC1_0__RegVSRC1_1, 0, { MCK_RegVSRC, MCK_RegVSR…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td577 "xvnegdp $XT, $XB", IIC_VecFP,