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Searched refs:xvrdpiz (Results 1 – 10 of 10) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dftrunc-vec.ll17 ; CHECK-NEXT: xvrdpiz 34, 34
37 ; CHECK-NEXT: xvrdpiz 34, 34
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dvsx.s425 # CHECK-BE: xvrdpiz 7, 27 # encoding: [0xf0,0xe0,0xdb,0x64]
426 # CHECK-LE: xvrdpiz 7, 27 # encoding: [0x64,0xdb,0xe0,0xf0]
427 xvrdpiz 7, 27
/external/llvm/test/MC/PowerPC/
Dvsx.s425 # CHECK-BE: xvrdpiz 7, 27 # encoding: [0xf0,0xe0,0xdb,0x64]
426 # CHECK-LE: xvrdpiz 7, 27 # encoding: [0x64,0xdb,0xe0,0xf0]
427 xvrdpiz 7, 27
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt420 # CHECK: xvrdpiz 7, 27
/external/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt420 # CHECK: xvrdpiz 7, 27
/external/v8/src/codegen/ppc/
Dconstants-ppc.h394 V(xvrdpiz, XVRDPIZ, 0xF0000364) \
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc3361 __ xvrdpiz(i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td673 "xvrdpiz $XT, $XB", IIC_VecFP,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4393 "dpip\007xvrdpiz\006xvredp\006xvresp\006xvrspi\007xvrspic\007xvrspim\007"
6894 …{ 13965 /* xvrdpiz */, PPC::XVRDPIZ, Convert__RegVSRC1_0__RegVSRC1_1, 0, { MCK_RegVSRC, MCK_RegVSR…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td748 "xvrdpiz $XT, $XB", IIC_VecFP,