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Searched refs:xvsubdp (Results 1 – 11 of 11) sorted by relevance

/external/llvm/test/CodeGen/PowerPC/
Dswaps-le-7.ll17 ; CHECK-NEXT: xvsubdp
20 ; CHECK-NEXT: xvsubdp
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dswaps-le-7.ll16 ; CHECK-DAG: xvsubdp
20 ; CHECK-DAG: xvsubdp
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dvsx.s461 # CHECK-BE: xvsubdp 7, 63, 27 # encoding: [0xf0,0xff,0xdb,0x44]
462 # CHECK-LE: xvsubdp 7, 63, 27 # encoding: [0x44,0xdb,0xff,0xf0]
463 xvsubdp 7, 63, 27
/external/llvm/test/MC/PowerPC/
Dvsx.s461 # CHECK-BE: xvsubdp 7, 63, 27 # encoding: [0xf0,0xff,0xdb,0x44]
462 # CHECK-LE: xvsubdp 7, 63, 27 # encoding: [0x44,0xdb,0xff,0xf0]
463 xvsubdp 7, 63, 27
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt456 # CHECK: xvsubdp 7, 63, 27
/external/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt456 # CHECK: xvsubdp 7, 63, 27
/external/v8/src/codegen/ppc/
Dconstants-ppc.h288 V(xvsubdp, XVSUBDP, 0xF0000340) \
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc2399 __ xvsubdp(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td182 "xvsubdp $XT, $XA, $XB", IIC_VecFP,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td226 "xvsubdp $XT, $XA, $XB", IIC_VecFP,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc6906 …{ 14066 /* xvsubdp */, PPC::XVSUBDP, Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2, 0, { MCK_RegVSRC…