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Searched refs:MC_SMMU_PPCS_ASID_0 (Results 1 – 2 of 2) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/include/t210/
Dtegra_def.h236 #define MC_SMMU_PPCS_ASID_0 0x270U macro
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/drivers/se/
Dsecurity_engine.c972 val = mmio_read_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0); in tegra_se_suspend()
974 mmio_write_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0, val); in tegra_se_suspend()