| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | add.ll | 113 ; GP32: sltu $[[T1:[0-9]+]], $3, $5
120 ; MM32: sltu $[[T1:[0-9]+]], $3, $5
137 ; PRE4: sltu $[[R7:[0-9]+]], $[[R6]], $7
142 ; PRE4: sltu $[[R7]], $[[R8]], $6
148 ; PRE4: sltu $[[R17:[0-9]+]], $[[R15]], $[[R13]]
149 ; PRE4: sltu $[[R18:[0-9]+]], $[[R13]], $[[R1]]
157 ; GP32-CMOV: sltu $[[T4:[0-9]+]], $[[T3]], $7
159 ; GP32-CMOV: sltu $[[T6:[0-9]+]], $[[T5]], $6
166 ; GP32-CMOV: sltu $[[T13:[0-9]+]], $[[T11]], $[[T10]]
168 ; GP32-CMOV: sltu $[[T15:[0-9]+]], $[[T10]], $5
[all …]
|
| D | sub.ll | 101 ; GP32-NOT-MM: sltu $[[T0:[0-9]+]], $5, $7
106 ; MM32: sltu $[[T0:[0-9]+]], $5, $7
123 ; PRE4: sltu $[[T2:[0-9]+]], $7, $[[T1]]
128 ; PRE4: sltu $[[T5]], $6, $[[T0]]
133 ; PRE4: sltu $[[T9:[0-9]+]], $[[T7]], $[[T5]]
134 ; PRE4: sltu $[[T10:[0-9]+]], $5, $[[T6]]
144 ; MMR3: sltu $[[T2:[0-9]+]], $6, $[[T1]]
147 ; MMR3: sltu $[[T5:[0-9]+]], $7, $[[T4]]
152 ; MMR3: sltu $[[T10:[0-9]+]], $[[T8]], $[[T2]]
153 ; MMR3: sltu $[[T11:[0-9]+]], $5, $[[T7]]
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | mips64-instalias-imm-expanding.s | 640 sltu $4, -0x80000000
642 # CHECK-NEXT: sltu $4, $4, $1 # encoding: [0x2b,0x20,0x81,0x00]
643 sltu $4, -0x8001
646 # CHECK-NEXT: sltu $4, $4, $1 # encoding: [0x2b,0x20,0x81,0x00]
647 sltu $4, -0x8000
649 sltu $4, 0
651 sltu $4, 0xFFFF
653 # CHECK-NEXT: sltu $4, $4, $1 # encoding: [0x2b,0x20,0x81,0x00]
654 sltu $4, 0x10000
656 # CHECK-NEXT: sltu $4, $4, $1 # encoding: [0x2b,0x20,0x81,0x00]
[all …]
|
| D | macro-bcc-imm.s | 61 # ALL: sltu $1, $6, $1
65 # ALL: sltu $1, $1, $6
69 # ALL: sltu $1, $6, $1
73 # ALL: sltu $1, $1, $6
93 # ALL: sltu $1, $6, $1
97 # ALL: sltu $1, $1, $6
101 # ALL: sltu $1, $6, $1
105 # ALL: sltu $1, $1, $6
|
| D | branch-pseudos.s | 31 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
36 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
74 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
79 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
123 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
128 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
171 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
176 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
282 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
287 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
[all …]
|
| D | instalias-imm-expanding.s | 619 sltu $4, $5, -0x80000000
621 # MIPS: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
624 # MICROMIPS: sltu $4, $4, $5 # encoding: [0xa4,0x00,0x90,0x23]
626 sltu $4, $5, -0x8001
629 # MIPS: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
634 # MICROMIPS: sltu $4, $4, $5 # encoding: [0xa4,0x00,0x90,0x23]
636 sltu $4, $5, -0x8000
641 sltu $4, $5, 0
646 sltu $4, $5, 0xFFFF
648 # MIPS: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
[all …]
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | add.ll | 108 ; GP32: sltu $[[T0:[0-9]+]], $3, $7
115 ; MM32: sltu $[[T0:[0-9]+]], $3, $7
131 ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
137 ; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
140 ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
147 ; GP64: sltu $[[T0:[0-9]+]], $3, $7
153 ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
157 ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
162 ; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]]
169 ; MM64: sltu $[[T0:[0-9]+]], $3, $7
[all …]
|
| D | sub.ll | 103 ; GP32: sltu $[[T0:[0-9]+]], $5, $7
118 ; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]]
125 ; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]]
128 ; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]]
134 ; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
141 ; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]]
144 ; GP32-MM: sltu $[[T2]], $7, $[[T4]]
150 ; GP64: sltu $[[T0:[0-9]+]], $5, $7
|
| /external/llvm/test/MC/Mips/ |
| D | macro-bcc-imm.s | 23 # ALL: sltu $1, $6, $1
27 # ALL: sltu $1, $1, $6
31 # ALL: sltu $1, $6, $1
35 # ALL: sltu $1, $1, $6
55 # ALL: sltu $1, $6, $1
59 # ALL: sltu $1, $1, $6
63 # ALL: sltu $1, $6, $1
67 # ALL: sltu $1, $1, $6
|
| D | instalias-imm-expanding.s | 209 sltu $4, $5, -0x80000000
211 # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
212 sltu $4, $5, -0x8001
215 # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
216 sltu $4, $5, -0x8000
218 sltu $4, $5, 0
220 sltu $4, $5, 0xFFFF
222 sltu $4, $5, 0x10000
224 # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
225 sltu $4, $5, 0xFFFFFFFF
|
| D | branch-pseudos.s | 31 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
36 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
74 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
79 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
123 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
128 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
171 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
176 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
282 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
287 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
[all …]
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | cond-branch.ll | 45 ; MIPS32-OM1: sltu {{.*}}, $zero, {{.*}}
129 ; MIPS32: sltu
132 ; MIPS32-OM1: sltu
146 ; MIPS32: sltu
149 ; MIPS32-OM1: sltu
164 ; MIPS32: sltu
167 ; MIPS32-OM1: sltu
181 ; MIPS32: sltu
184 ; MIPS32-OM1: sltu
|
| D | vector-icmp.ll | 96 ; MIPS32: sltu [[T4]],zero,[[T4]]
98 ; MIPS32: sltu [[T5]],zero,[[T5]]
100 ; MIPS32: sltu [[T6]],zero,[[T6]]
102 ; MIPS32: sltu [[T7]],zero,[[T7]]
189 ; MIPS32: sltu [[T4:.*]],a0,[[T0]]
191 ; MIPS32: sltu [[T5:.*]],a1,[[T1]]
193 ; MIPS32: sltu [[T6:.*]],a2,[[T2]]
195 ; MIPS32: sltu [[T7:.*]],a3,[[T3]]
216 ; MIPS32: sltu v0,[[T0]],[[T4:.*]]
217 ; MIPS32: sltu v1,[[T1]],[[T5:.*]]
[all …]
|
| D | icmp.ll | 32 ; MIPS32: sltu {{.*}}, $zero, {{.*}}
50 ; MIPS32: sltu
69 ; MIPS32: sltu
88 ; MIPS32: sltu
107 ; MIPS32: sltu
148 ; MIPS32: sltu
174 ; MIPS32: sltu
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | sel1.ll | 10 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
27 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
44 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
59 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
75 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
91 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
|
| D | icmpa.ll | 47 ; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
48 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
67 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
68 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
87 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
88 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
106 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
108 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
126 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
128 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | sel1.ll | 27 ; CHECK-NEXT: sltu $1, $zero, $1
45 ; CHECK-NEXT: sltu $1, $zero, $1
61 ; CHECK-NEXT: sltu $1, $zero, $1
78 ; CHECK-NEXT: sltu $1, $zero, $1
93 ; CHECK-NEXT: sltu $1, $zero, $1
110 ; CHECK-NEXT: sltu $1, $zero, $1
126 ; CHECK-NEXT: sltu $1, $zero, $1
|
| D | icmpa.ll | 47 ; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
48 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
67 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
68 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
87 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
88 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
106 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
108 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
126 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
128 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | setcc-se.ll | 19 ; CHECK: sltu ${{[0-9]+}}, $zero, $4
20 ; MMR6: sltu ${{[0-9]+}}, $zero, $4
124 ; CHECK: sltu ${{[0-9]+}}
125 ; MMR6: sltu ${{[0-9]+}}
161 ; CHECK: sltu ${{[0-9]+}}
162 ; MMR6: sltu ${{[0-9]+}}
|
| D | const-mult.ll | 70 ; MIPS32-NEXT: sltu $1, $2, $1
97 ; MIPS32-NEXT: sltu $1, $2, $1
103 ; MIPS32-NEXT: sltu $9, $3, $8
111 ; MIPS32-NEXT: sltu $5, $8, $5
118 ; MIPS32-NEXT: sltu $6, $1, $8
132 ; MIPS64-NEXT: sltu $3, $2, $3
149 ; MIPS32-NEXT: sltu $1, $2, $1
155 ; MIPS32-NEXT: sltu $9, $8, $3
157 ; MIPS32-NEXT: sltu $10, $zero, $8
158 ; MIPS32-NEXT: sltu $11, $zero, $2
[all …]
|
| D | llcarry.ll | 18 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
30 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
43 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
| D | 2008-06-05-Carry.ll | 7 ; CHECK-DAG: sltu
17 ; CHECK-DAG: sltu
|
| /external/llvm/test/CodeGen/Mips/ |
| D | llcarry.ll | 17 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
30 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
43 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
| D | 2008-06-05-Carry.ll | 6 ; CHECK: sltu
17 ; CHECK: sltu
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/ |
| D | i32-icmp.ll | 33 ; RV32I-NEXT: sltu a0, a1, a0
43 ; RV32I-NEXT: sltu a0, a0, a1
54 ; RV32I-NEXT: sltu a0, a0, a1
64 ; RV32I-NEXT: sltu a0, a1, a0
|