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Searched refs:spsr_irq (Results 1 – 10 of 10) sorted by relevance

/external/arm-trusted-firmware/include/arch/aarch32/
Dsmccc_macros.S65 mrs r6, spsr_irq
207 msr spsr_irq, r6
Dsmccc_helpers.h55 u_register_t spsr_irq; member
/external/llvm/test/MC/ARM/
Dmove-banked-regs.s53 mrs r1, spsr_irq
163 msr spsr_irq, r11
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dmove-banked-regs.s53 mrs r1, spsr_irq
163 msr spsr_irq, r11
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenSystemRegister.inc32 spsr_irq = 29,
115 { "spsr_irq", 0x30 }, // 27
/external/arm-trusted-firmware/lib/el3_runtime/aarch64/
Dcontext.S81 mrs x13, spsr_irq
179 msr spsr_irq, x13
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMSystemRegister.td151 def : BankedReg<"spsr_irq", 0x30>;
/external/arm-trusted-firmware/bl31/aarch64/
Dcrash_reporting.S298 mrs x12, spsr_irq
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs1570 0x0c,0x43,0x1c,0xd5 = msr spsr_irq, x12
1882 0x09,0x43,0x3c,0xd5 = mrs x9, spsr_irq
/external/arm-trusted-firmware/docs/design/
Dfirmware-design.rst1227 spsr_irq :0x0000000000000000