1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef IPA_QMI_SERVICE_V01_H 20 #define IPA_QMI_SERVICE_V01_H 21 #include <linux/types.h> 22 #define QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01 6 23 #define QMI_IPA_MAX_FILTERS_EX_V01 128 24 #define QMI_IPA_MAX_FILTERS_EX2_V01 256 25 #define QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01 2 26 #define QMI_IPA_MAX_FILTERS_V01 64 27 #define QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01 2 28 #define QMI_IPA_ENDP_DESC_NUM_MAX_V01 31 29 #define QMI_IPA_MAX_APN_V01 8 30 #define QMI_IPA_MAX_CLIENT_DST_PIPES_V01 8 31 #define QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01 2 32 #define QMI_IPA_MAX_UL_FIREWALL_RULES_V01 64 33 #define QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01 6 34 #define QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01 2 35 #define QMI_IPA_MAX_PIPES_V01 20 36 #define QMI_IPA_MAX_PER_CLIENTS_V01 64 37 #define IPA_QMI_SUPPORTS_STATS 38 #define IPA_QMI_SUPPORT_MHI_DEFAULT 39 #define IPA_INT_MAX ((int) (~0U >> 1)) 40 #define IPA_INT_MIN (- IPA_INT_MAX - 1) 41 enum ipa_qmi_result_type_v01 { 42 IPA_QMI_RESULT_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 43 IPA_QMI_RESULT_SUCCESS_V01 = 0, 44 IPA_QMI_RESULT_FAILURE_V01 = 1, 45 IPA_QMI_RESULT_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 46 }; 47 enum ipa_qmi_error_type_v01 { 48 IPA_QMI_ERROR_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 49 IPA_QMI_ERR_NONE_V01 = 0x0000, 50 IPA_QMI_ERR_MALFORMED_MSG_V01 = 0x0001, 51 IPA_QMI_ERR_NO_MEMORY_V01 = 0x0002, 52 IPA_QMI_ERR_INTERNAL_V01 = 0x0003, 53 IPA_QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 = 0x0005, 54 IPA_QMI_ERR_INVALID_ID_V01 = 0x0029, 55 IPA_QMI_ERR_ENCODING_V01 = 0x003A, 56 IPA_QMI_ERR_INCOMPATIBLE_STATE_V01 = 0x005A, 57 IPA_QMI_ERR_NOT_SUPPORTED_V01 = 0x005E, 58 IPA_QMI_ERROR_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 59 }; 60 struct ipa_qmi_response_type_v01 { 61 uint16_t result; 62 uint16_t error; 63 }; 64 enum ipa_platform_type_enum_v01 { 65 IPA_PLATFORM_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 66 QMI_IPA_PLATFORM_TYPE_INVALID_V01 = 0, 67 QMI_IPA_PLATFORM_TYPE_TN_V01 = 1, 68 QMI_IPA_PLATFORM_TYPE_LE_V01 = 2, 69 QMI_IPA_PLATFORM_TYPE_MSM_ANDROID_V01 = 3, 70 QMI_IPA_PLATFORM_TYPE_MSM_WINDOWS_V01 = 4, 71 QMI_IPA_PLATFORM_TYPE_MSM_QNX_V01 = 5, 72 QMI_IPA_PLATFORM_TYPE_LE_MHI_V01 = 6, 73 IPA_PLATFORM_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 74 }; 75 #define QMI_IPA_PLATFORM_TYPE_LE_MHI_V01 QMI_IPA_PLATFORM_TYPE_LE_MHI_V01 76 struct ipa_hdr_tbl_info_type_v01 { 77 uint32_t modem_offset_start; 78 uint32_t modem_offset_end; 79 }; 80 struct ipa_route_tbl_info_type_v01 { 81 uint32_t route_tbl_start_addr; 82 uint32_t num_indices; 83 }; 84 struct ipa_modem_mem_info_type_v01 { 85 uint32_t block_start_addr; 86 uint32_t size; 87 }; 88 struct ipa_hdr_proc_ctx_tbl_info_type_v01 { 89 uint32_t modem_offset_start; 90 uint32_t modem_offset_end; 91 }; 92 struct ipa_zip_tbl_info_type_v01 { 93 uint32_t modem_offset_start; 94 uint32_t modem_offset_end; 95 }; 96 struct ipa_init_modem_driver_req_msg_v01 { 97 uint8_t platform_type_valid; 98 enum ipa_platform_type_enum_v01 platform_type; 99 uint8_t hdr_tbl_info_valid; 100 struct ipa_hdr_tbl_info_type_v01 hdr_tbl_info; 101 uint8_t v4_route_tbl_info_valid; 102 struct ipa_route_tbl_info_type_v01 v4_route_tbl_info; 103 uint8_t v6_route_tbl_info_valid; 104 struct ipa_route_tbl_info_type_v01 v6_route_tbl_info; 105 uint8_t v4_filter_tbl_start_addr_valid; 106 uint32_t v4_filter_tbl_start_addr; 107 uint8_t v6_filter_tbl_start_addr_valid; 108 uint32_t v6_filter_tbl_start_addr; 109 uint8_t modem_mem_info_valid; 110 struct ipa_modem_mem_info_type_v01 modem_mem_info; 111 uint8_t ctrl_comm_dest_end_pt_valid; 112 uint32_t ctrl_comm_dest_end_pt; 113 uint8_t is_ssr_bootup_valid; 114 uint8_t is_ssr_bootup; 115 uint8_t hdr_proc_ctx_tbl_info_valid; 116 struct ipa_hdr_proc_ctx_tbl_info_type_v01 hdr_proc_ctx_tbl_info; 117 uint8_t zip_tbl_info_valid; 118 struct ipa_zip_tbl_info_type_v01 zip_tbl_info; 119 uint8_t v4_hash_route_tbl_info_valid; 120 struct ipa_route_tbl_info_type_v01 v4_hash_route_tbl_info; 121 uint8_t v6_hash_route_tbl_info_valid; 122 struct ipa_route_tbl_info_type_v01 v6_hash_route_tbl_info; 123 uint8_t v4_hash_filter_tbl_start_addr_valid; 124 uint32_t v4_hash_filter_tbl_start_addr; 125 uint8_t v6_hash_filter_tbl_start_addr_valid; 126 uint32_t v6_hash_filter_tbl_start_addr; 127 uint8_t hw_stats_quota_base_addr_valid; 128 uint32_t hw_stats_quota_base_addr; 129 uint8_t hw_stats_quota_size_valid; 130 uint32_t hw_stats_quota_size; 131 uint8_t hw_drop_stats_base_addr_valid; 132 uint32_t hw_drop_stats_base_addr; 133 uint8_t hw_drop_stats_table_size_valid; 134 uint32_t hw_drop_stats_table_size; 135 }; 136 struct ipa_init_modem_driver_resp_msg_v01 { 137 struct ipa_qmi_response_type_v01 resp; 138 uint8_t ctrl_comm_dest_end_pt_valid; 139 uint32_t ctrl_comm_dest_end_pt; 140 uint8_t default_end_pt_valid; 141 uint32_t default_end_pt; 142 uint8_t modem_driver_init_pending_valid; 143 uint8_t modem_driver_init_pending; 144 }; 145 struct ipa_init_modem_driver_cmplt_req_msg_v01 { 146 uint8_t status; 147 }; 148 struct ipa_init_modem_driver_cmplt_resp_msg_v01 { 149 struct ipa_qmi_response_type_v01 resp; 150 }; 151 struct ipa_indication_reg_req_msg_v01 { 152 uint8_t master_driver_init_complete_valid; 153 uint8_t master_driver_init_complete; 154 uint8_t data_usage_quota_reached_valid; 155 uint8_t data_usage_quota_reached; 156 uint8_t ipa_mhi_ready_ind_valid; 157 uint8_t ipa_mhi_ready_ind; 158 uint8_t endpoint_desc_ind_valid; 159 uint8_t endpoint_desc_ind; 160 uint8_t bw_change_ind_valid; 161 uint8_t bw_change_ind; 162 }; 163 struct ipa_indication_reg_resp_msg_v01 { 164 struct ipa_qmi_response_type_v01 resp; 165 }; 166 struct ipa_master_driver_init_complt_ind_msg_v01 { 167 struct ipa_qmi_response_type_v01 master_driver_init_status; 168 }; 169 struct ipa_ipfltr_range_eq_16_type_v01 { 170 uint8_t offset; 171 uint16_t range_low; 172 uint16_t range_high; 173 }; 174 struct ipa_ipfltr_mask_eq_32_type_v01 { 175 uint8_t offset; 176 uint32_t mask; 177 uint32_t value; 178 }; 179 struct ipa_ipfltr_eq_16_type_v01 { 180 uint8_t offset; 181 uint16_t value; 182 }; 183 struct ipa_ipfltr_eq_32_type_v01 { 184 uint8_t offset; 185 uint32_t value; 186 }; 187 struct ipa_ipfltr_mask_eq_128_type_v01 { 188 uint8_t offset; 189 uint8_t mask[16]; 190 uint8_t value[16]; 191 }; 192 struct ipa_filter_rule_type_v01 { 193 uint16_t rule_eq_bitmap; 194 uint8_t tos_eq_present; 195 uint8_t tos_eq; 196 uint8_t protocol_eq_present; 197 uint8_t protocol_eq; 198 uint8_t num_ihl_offset_range_16; 199 struct ipa_ipfltr_range_eq_16_type_v01 ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; 200 uint8_t num_offset_meq_32; 201 struct ipa_ipfltr_mask_eq_32_type_v01 offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; 202 uint8_t tc_eq_present; 203 uint8_t tc_eq; 204 uint8_t flow_eq_present; 205 uint32_t flow_eq; 206 uint8_t ihl_offset_eq_16_present; 207 struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; 208 uint8_t ihl_offset_eq_32_present; 209 struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; 210 uint8_t num_ihl_offset_meq_32; 211 struct ipa_ipfltr_mask_eq_32_type_v01 ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; 212 uint8_t num_offset_meq_128; 213 struct ipa_ipfltr_mask_eq_128_type_v01 offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; 214 uint8_t metadata_meq32_present; 215 struct ipa_ipfltr_mask_eq_32_type_v01 metadata_meq32; 216 uint8_t ipv4_frag_eq_present; 217 }; 218 struct ipa_filter_rule_req2_type_v01 { 219 uint16_t rule_eq_bitmap; 220 uint8_t pure_ack_eq_present; 221 uint8_t pure_ack_eq; 222 uint8_t protocol_eq_present; 223 uint8_t protocol_eq; 224 uint8_t num_ihl_offset_range_16; 225 struct ipa_ipfltr_range_eq_16_type_v01 ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; 226 uint8_t num_offset_meq_32; 227 struct ipa_ipfltr_mask_eq_32_type_v01 offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; 228 uint8_t tc_eq_present; 229 uint8_t tc_eq; 230 uint8_t flow_eq_present; 231 uint32_t flow_eq; 232 uint8_t ihl_offset_eq_16_present; 233 struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; 234 uint8_t ihl_offset_eq_32_present; 235 struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; 236 uint8_t num_ihl_offset_meq_32; 237 struct ipa_ipfltr_mask_eq_32_type_v01 ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; 238 uint8_t num_offset_meq_128; 239 struct ipa_ipfltr_mask_eq_128_type_v01 offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; 240 uint8_t metadata_meq32_present; 241 struct ipa_ipfltr_mask_eq_32_type_v01 metadata_meq32; 242 uint8_t ipv4_frag_eq_present; 243 }; 244 enum ipa_ip_type_enum_v01 { 245 IPA_IP_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 246 QMI_IPA_IP_TYPE_INVALID_V01 = 0, 247 QMI_IPA_IP_TYPE_V4_V01 = 1, 248 QMI_IPA_IP_TYPE_V6_V01 = 2, 249 QMI_IPA_IP_TYPE_V4V6_V01 = 3, 250 IPA_IP_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 251 }; 252 enum ipa_filter_action_enum_v01 { 253 IPA_FILTER_ACTION_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 254 QMI_IPA_FILTER_ACTION_INVALID_V01 = 0, 255 QMI_IPA_FILTER_ACTION_SRC_NAT_V01 = 1, 256 QMI_IPA_FILTER_ACTION_DST_NAT_V01 = 2, 257 QMI_IPA_FILTER_ACTION_ROUTING_V01 = 3, 258 QMI_IPA_FILTER_ACTION_EXCEPTION_V01 = 4, 259 IPA_FILTER_ACTION_ENUM_MAX_ENUM_VAL_V01 = 2147483647 260 }; 261 struct ipa_filter_spec_type_v01 { 262 uint32_t filter_spec_identifier; 263 enum ipa_ip_type_enum_v01 ip_type; 264 struct ipa_filter_rule_type_v01 filter_rule; 265 enum ipa_filter_action_enum_v01 filter_action; 266 uint8_t is_routing_table_index_valid; 267 uint32_t route_table_index; 268 uint8_t is_mux_id_valid; 269 uint32_t mux_id; 270 }; 271 struct ipa_filter_spec_ex_type_v01 { 272 enum ipa_ip_type_enum_v01 ip_type; 273 struct ipa_filter_rule_type_v01 filter_rule; 274 enum ipa_filter_action_enum_v01 filter_action; 275 uint8_t is_routing_table_index_valid; 276 uint32_t route_table_index; 277 uint8_t is_mux_id_valid; 278 uint32_t mux_id; 279 uint32_t rule_id; 280 uint8_t is_rule_hashable; 281 }; 282 struct ipa_filter_spec_ex2_type_v01 { 283 enum ipa_ip_type_enum_v01 ip_type; 284 struct ipa_filter_rule_req2_type_v01 filter_rule; 285 enum ipa_filter_action_enum_v01 filter_action; 286 uint8_t is_routing_table_index_valid; 287 uint32_t route_table_index; 288 uint8_t is_mux_id_valid; 289 uint32_t mux_id; 290 uint32_t rule_id; 291 uint8_t is_rule_hashable; 292 }; 293 struct ipa_install_fltr_rule_req_msg_v01 { 294 uint8_t filter_spec_list_valid; 295 uint32_t filter_spec_list_len; 296 struct ipa_filter_spec_type_v01 filter_spec_list[QMI_IPA_MAX_FILTERS_V01]; 297 uint8_t source_pipe_index_valid; 298 uint32_t source_pipe_index; 299 uint8_t num_ipv4_filters_valid; 300 uint32_t num_ipv4_filters; 301 uint8_t num_ipv6_filters_valid; 302 uint32_t num_ipv6_filters; 303 uint8_t xlat_filter_indices_list_valid; 304 uint32_t xlat_filter_indices_list_len; 305 uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; 306 uint8_t filter_spec_ex_list_valid; 307 uint32_t filter_spec_ex_list_len; 308 struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_V01]; 309 uint8_t filter_spec_ex2_list_valid; 310 uint32_t filter_spec_ex2_list_len; 311 struct ipa_filter_spec_ex2_type_v01 filter_spec_ex2_list[QMI_IPA_MAX_FILTERS_V01]; 312 uint8_t ul_firewall_indices_list_valid; 313 uint32_t ul_firewall_indices_list_len; 314 uint32_t ul_firewall_indices_list[QMI_IPA_MAX_FILTERS_V01]; 315 }; 316 struct ipa_filter_rule_identifier_to_handle_map_v01 { 317 uint32_t filter_spec_identifier; 318 uint32_t filter_handle; 319 }; 320 struct ipa_install_fltr_rule_resp_msg_v01 { 321 struct ipa_qmi_response_type_v01 resp; 322 uint8_t filter_handle_list_valid; 323 uint32_t filter_handle_list_len; 324 struct ipa_filter_rule_identifier_to_handle_map_v01 filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; 325 uint8_t rule_id_valid; 326 uint32_t rule_id_len; 327 uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; 328 }; 329 struct ipa_filter_handle_to_index_map_v01 { 330 uint32_t filter_handle; 331 uint32_t filter_index; 332 }; 333 struct ipa_fltr_installed_notif_req_msg_v01 { 334 uint32_t source_pipe_index; 335 enum ipa_qmi_result_type_v01 install_status; 336 uint32_t filter_index_list_len; 337 struct ipa_filter_handle_to_index_map_v01 filter_index_list[QMI_IPA_MAX_FILTERS_V01]; 338 uint8_t embedded_pipe_index_valid; 339 uint32_t embedded_pipe_index; 340 uint8_t retain_header_valid; 341 uint8_t retain_header; 342 uint8_t embedded_call_mux_id_valid; 343 uint32_t embedded_call_mux_id; 344 uint8_t num_ipv4_filters_valid; 345 uint32_t num_ipv4_filters; 346 uint8_t num_ipv6_filters_valid; 347 uint32_t num_ipv6_filters; 348 uint8_t start_ipv4_filter_idx_valid; 349 uint32_t start_ipv4_filter_idx; 350 uint8_t start_ipv6_filter_idx_valid; 351 uint32_t start_ipv6_filter_idx; 352 uint8_t rule_id_valid; 353 uint32_t rule_id_len; 354 uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; 355 uint8_t dst_pipe_id_valid; 356 uint32_t dst_pipe_id_len; 357 uint32_t dst_pipe_id[QMI_IPA_MAX_CLIENT_DST_PIPES_V01]; 358 uint8_t rule_id_ex_valid; 359 uint32_t rule_id_ex_len; 360 uint32_t rule_id_ex[QMI_IPA_MAX_FILTERS_EX2_V01]; 361 }; 362 struct ipa_fltr_installed_notif_resp_msg_v01 { 363 struct ipa_qmi_response_type_v01 resp; 364 }; 365 struct ipa_enable_force_clear_datapath_req_msg_v01 { 366 uint32_t source_pipe_bitmask; 367 uint32_t request_id; 368 uint8_t throttle_source_valid; 369 uint8_t throttle_source; 370 }; 371 struct ipa_enable_force_clear_datapath_resp_msg_v01 { 372 struct ipa_qmi_response_type_v01 resp; 373 }; 374 struct ipa_disable_force_clear_datapath_req_msg_v01 { 375 uint32_t request_id; 376 }; 377 struct ipa_disable_force_clear_datapath_resp_msg_v01 { 378 struct ipa_qmi_response_type_v01 resp; 379 }; 380 enum ipa_peripheral_speed_enum_v01 { 381 IPA_PERIPHERAL_SPEED_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 382 QMI_IPA_PER_USB_FS_V01 = 1, 383 QMI_IPA_PER_USB_HS_V01 = 2, 384 QMI_IPA_PER_USB_SS_V01 = 3, 385 QMI_IPA_PER_WLAN_V01 = 4, 386 IPA_PERIPHERAL_SPEED_ENUM_MAX_ENUM_VAL_V01 = 2147483647 387 }; 388 enum ipa_pipe_mode_enum_v01 { 389 IPA_PIPE_MODE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 390 QMI_IPA_PIPE_MODE_HW_V01 = 1, 391 QMI_IPA_PIPE_MODE_SW_V01 = 2, 392 IPA_PIPE_MODE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 393 }; 394 enum ipa_peripheral_type_enum_v01 { 395 IPA_PERIPHERAL_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 396 QMI_IPA_PERIPHERAL_USB_V01 = 1, 397 QMI_IPA_PERIPHERAL_HSIC_V01 = 2, 398 QMI_IPA_PERIPHERAL_PCIE_V01 = 3, 399 IPA_PERIPHERAL_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 400 }; 401 struct ipa_config_req_msg_v01 { 402 uint8_t peripheral_type_valid; 403 enum ipa_peripheral_type_enum_v01 peripheral_type; 404 uint8_t hw_deaggr_supported_valid; 405 uint8_t hw_deaggr_supported; 406 uint8_t max_aggr_frame_size_valid; 407 uint32_t max_aggr_frame_size; 408 uint8_t ipa_ingress_pipe_mode_valid; 409 enum ipa_pipe_mode_enum_v01 ipa_ingress_pipe_mode; 410 uint8_t peripheral_speed_info_valid; 411 enum ipa_peripheral_speed_enum_v01 peripheral_speed_info; 412 uint8_t dl_accumulation_time_limit_valid; 413 uint32_t dl_accumulation_time_limit; 414 uint8_t dl_accumulation_pkt_limit_valid; 415 uint32_t dl_accumulation_pkt_limit; 416 uint8_t dl_accumulation_byte_limit_valid; 417 uint32_t dl_accumulation_byte_limit; 418 uint8_t ul_accumulation_time_limit_valid; 419 uint32_t ul_accumulation_time_limit; 420 uint8_t hw_control_flags_valid; 421 uint32_t hw_control_flags; 422 uint8_t ul_msi_event_threshold_valid; 423 uint32_t ul_msi_event_threshold; 424 uint8_t dl_msi_event_threshold_valid; 425 uint32_t dl_msi_event_threshold; 426 uint8_t ul_fifo_size_valid; 427 uint32_t ul_fifo_size; 428 uint8_t dl_fifo_size_valid; 429 uint32_t dl_fifo_size; 430 uint8_t dl_buf_size_valid; 431 uint32_t dl_buf_size; 432 }; 433 struct ipa_config_resp_msg_v01 { 434 struct ipa_qmi_response_type_v01 resp; 435 }; 436 enum ipa_stats_type_enum_v01 { 437 IPA_STATS_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 438 QMI_IPA_STATS_TYPE_INVALID_V01 = 0, 439 QMI_IPA_STATS_TYPE_PIPE_V01 = 1, 440 QMI_IPA_STATS_TYPE_FILTER_RULES_V01 = 2, 441 IPA_STATS_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 442 }; 443 struct ipa_pipe_stats_info_type_v01 { 444 uint32_t pipe_index; 445 uint64_t num_ipv4_packets; 446 uint64_t num_ipv4_bytes; 447 uint64_t num_ipv6_packets; 448 uint64_t num_ipv6_bytes; 449 }; 450 struct ipa_stats_type_filter_rule_v01 { 451 uint32_t filter_rule_index; 452 uint64_t num_packets; 453 }; 454 struct ipa_get_data_stats_req_msg_v01 { 455 enum ipa_stats_type_enum_v01 ipa_stats_type; 456 uint8_t reset_stats_valid; 457 uint8_t reset_stats; 458 }; 459 struct ipa_get_data_stats_resp_msg_v01 { 460 struct ipa_qmi_response_type_v01 resp; 461 uint8_t ipa_stats_type_valid; 462 enum ipa_stats_type_enum_v01 ipa_stats_type; 463 uint8_t ul_src_pipe_stats_list_valid; 464 uint32_t ul_src_pipe_stats_list_len; 465 struct ipa_pipe_stats_info_type_v01 ul_src_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; 466 uint8_t dl_dst_pipe_stats_list_valid; 467 uint32_t dl_dst_pipe_stats_list_len; 468 struct ipa_pipe_stats_info_type_v01 dl_dst_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; 469 uint8_t dl_filter_rule_stats_list_valid; 470 uint32_t dl_filter_rule_stats_list_len; 471 struct ipa_stats_type_filter_rule_v01 dl_filter_rule_stats_list[QMI_IPA_MAX_FILTERS_V01]; 472 }; 473 struct ipa_apn_data_stats_info_type_v01 { 474 uint32_t mux_id; 475 uint64_t num_ul_packets; 476 uint64_t num_ul_bytes; 477 uint64_t num_dl_packets; 478 uint64_t num_dl_bytes; 479 }; 480 struct ipa_get_apn_data_stats_req_msg_v01 { 481 uint8_t mux_id_list_valid; 482 uint32_t mux_id_list_len; 483 uint32_t mux_id_list[QMI_IPA_MAX_APN_V01]; 484 }; 485 struct ipa_get_apn_data_stats_resp_msg_v01 { 486 struct ipa_qmi_response_type_v01 resp; 487 uint8_t apn_data_stats_list_valid; 488 uint32_t apn_data_stats_list_len; 489 struct ipa_apn_data_stats_info_type_v01 apn_data_stats_list[QMI_IPA_MAX_APN_V01]; 490 }; 491 struct ipa_data_usage_quota_info_type_v01 { 492 uint32_t mux_id; 493 uint64_t num_Mbytes; 494 }; 495 struct ipa_set_data_usage_quota_req_msg_v01 { 496 uint8_t apn_quota_list_valid; 497 uint32_t apn_quota_list_len; 498 struct ipa_data_usage_quota_info_type_v01 apn_quota_list[QMI_IPA_MAX_APN_V01]; 499 }; 500 struct ipa_set_data_usage_quota_resp_msg_v01 { 501 struct ipa_qmi_response_type_v01 resp; 502 }; 503 struct ipa_data_usage_quota_reached_ind_msg_v01 { 504 struct ipa_data_usage_quota_info_type_v01 apn; 505 }; 506 struct ipa_stop_data_usage_quota_req_msg_v01 { 507 char __placeholder; 508 }; 509 struct ipa_stop_data_usage_quota_resp_msg_v01 { 510 struct ipa_qmi_response_type_v01 resp; 511 }; 512 struct ipa_install_fltr_rule_req_ex_msg_v01 { 513 uint8_t filter_spec_ex_list_valid; 514 uint32_t filter_spec_ex_list_len; 515 struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_EX_V01]; 516 uint8_t source_pipe_index_valid; 517 uint32_t source_pipe_index; 518 uint8_t num_ipv4_filters_valid; 519 uint32_t num_ipv4_filters; 520 uint8_t num_ipv6_filters_valid; 521 uint32_t num_ipv6_filters; 522 uint8_t xlat_filter_indices_list_valid; 523 uint32_t xlat_filter_indices_list_len; 524 uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_EX_V01]; 525 uint8_t filter_spec_ex2_list_valid; 526 uint32_t filter_spec_ex2_list_len; 527 struct ipa_filter_spec_ex2_type_v01 filter_spec_ex2_list[QMI_IPA_MAX_FILTERS_V01]; 528 uint8_t ul_firewall_indices_list_valid; 529 uint32_t ul_firewall_indices_list_len; 530 uint32_t ul_firewall_indices_list[QMI_IPA_MAX_FILTERS_V01]; 531 }; 532 struct ipa_install_fltr_rule_resp_ex_msg_v01 { 533 struct ipa_qmi_response_type_v01 resp; 534 uint8_t rule_id_valid; 535 uint32_t rule_id_len; 536 uint32_t rule_id[QMI_IPA_MAX_FILTERS_EX_V01]; 537 }; 538 struct ipa_enable_per_client_stats_req_msg_v01 { 539 uint8_t enable_per_client_stats; 540 }; 541 struct ipa_enable_per_client_stats_resp_msg_v01 { 542 struct ipa_qmi_response_type_v01 resp; 543 }; 544 struct ipa_per_client_stats_info_type_v01 { 545 uint32_t client_id; 546 uint32_t src_pipe_id; 547 uint64_t num_ul_ipv4_bytes; 548 uint64_t num_ul_ipv6_bytes; 549 uint64_t num_dl_ipv4_bytes; 550 uint64_t num_dl_ipv6_bytes; 551 uint32_t num_ul_ipv4_pkts; 552 uint32_t num_ul_ipv6_pkts; 553 uint32_t num_dl_ipv4_pkts; 554 uint32_t num_dl_ipv6_pkts; 555 }; 556 struct ipa_get_stats_per_client_req_msg_v01 { 557 uint32_t client_id; 558 uint32_t src_pipe_id; 559 uint8_t reset_stats_valid; 560 uint8_t reset_stats; 561 }; 562 struct ipa_get_stats_per_client_resp_msg_v01 { 563 struct ipa_qmi_response_type_v01 resp; 564 uint8_t per_client_stats_list_valid; 565 uint32_t per_client_stats_list_len; 566 struct ipa_per_client_stats_info_type_v01 per_client_stats_list[QMI_IPA_MAX_PER_CLIENTS_V01]; 567 }; 568 struct ipa_ul_firewall_rule_type_v01 { 569 enum ipa_ip_type_enum_v01 ip_type; 570 struct ipa_filter_rule_type_v01 filter_rule; 571 }; 572 struct ipa_configure_ul_firewall_rules_req_msg_v01 { 573 uint32_t firewall_rules_list_len; 574 struct ipa_ul_firewall_rule_type_v01 firewall_rules_list[QMI_IPA_MAX_UL_FIREWALL_RULES_V01]; 575 uint32_t mux_id; 576 uint8_t disable_valid; 577 uint8_t disable; 578 uint8_t are_blacklist_filters_valid; 579 uint8_t are_blacklist_filters; 580 }; 581 struct ipa_configure_ul_firewall_rules_resp_msg_v01 { 582 struct ipa_qmi_response_type_v01 resp; 583 }; 584 enum ipa_ul_firewall_status_enum_v01 { 585 IPA_UL_FIREWALL_STATUS_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 586 QMI_IPA_UL_FIREWALL_STATUS_SUCCESS_V01 = 0, 587 QMI_IPA_UL_FIREWALL_STATUS_FAILURE_V01 = 1, 588 IPA_UL_FIREWALL_STATUS_ENUM_MAX_ENUM_VAL_V01 = 2147483647 589 }; 590 struct ipa_ul_firewall_config_result_type_v01 { 591 enum ipa_ul_firewall_status_enum_v01 is_success; 592 uint32_t mux_id; 593 }; 594 struct ipa_configure_ul_firewall_rules_ind_msg_v01 { 595 struct ipa_ul_firewall_config_result_type_v01 result; 596 }; 597 struct ipa_mhi_ch_init_info_type_v01 { 598 uint8_t ch_id; 599 uint8_t er_id; 600 uint32_t ch_doorbell_addr; 601 uint32_t er_doorbell_addr; 602 uint32_t direction_type; 603 }; 604 struct ipa_mhi_smmu_info_type_v01 { 605 uint64_t iova_ctl_base_addr; 606 uint64_t iova_ctl_size; 607 uint64_t iova_data_base_addr; 608 uint64_t iova_data_size; 609 }; 610 struct ipa_mhi_ready_indication_msg_v01 { 611 uint32_t ch_info_arr_len; 612 struct ipa_mhi_ch_init_info_type_v01 ch_info_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; 613 uint8_t smmu_info_valid; 614 struct ipa_mhi_smmu_info_type_v01 smmu_info; 615 }; 616 #define IPA_MHI_READY_INDICATION_MSG_V01_MAX_MSG_LEN 123 617 struct ipa_mhi_mem_addr_info_type_v01 { 618 uint64_t pa; 619 uint64_t iova; 620 uint64_t size; 621 }; 622 enum ipa_mhi_brst_mode_enum_v01 { 623 IPA_MHI_BRST_MODE_ENUM_MIN_VAL_V01 = IPA_INT_MIN, 624 QMI_IPA_BURST_MODE_DEFAULT_V01 = 0, 625 QMI_IPA_BURST_MODE_ENABLED_V01 = 1, 626 QMI_IPA_BURST_MODE_DISABLED_V01 = 2, 627 IPA_MHI_BRST_MODE_ENUM_MAX_VAL_V01 = IPA_INT_MAX, 628 }; 629 struct ipa_mhi_tr_info_type_v01 { 630 uint8_t ch_id; 631 uint16_t poll_cfg; 632 enum ipa_mhi_brst_mode_enum_v01 brst_mode_type; 633 uint64_t ring_iova; 634 uint64_t ring_len; 635 uint64_t rp; 636 uint64_t wp; 637 }; 638 struct ipa_mhi_er_info_type_v01 { 639 uint8_t er_id; 640 uint32_t intmod_cycles; 641 uint32_t intmod_count; 642 uint32_t msi_addr; 643 uint64_t ring_iova; 644 uint64_t ring_len; 645 uint64_t rp; 646 uint64_t wp; 647 }; 648 struct ipa_mhi_alloc_channel_req_msg_v01 { 649 uint32_t tr_info_arr_len; 650 struct ipa_mhi_tr_info_type_v01 tr_info_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; 651 uint32_t er_info_arr_len; 652 struct ipa_mhi_er_info_type_v01 er_info_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; 653 uint32_t ctrl_addr_map_info_len; 654 struct ipa_mhi_mem_addr_info_type_v01 ctrl_addr_map_info[QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01]; 655 uint32_t data_addr_map_info_len; 656 struct ipa_mhi_mem_addr_info_type_v01 data_addr_map_info[QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01]; 657 }; 658 #define IPA_MHI_ALLOC_CHANNEL_REQ_MSG_V01_MAX_MSG_LEN 808 659 struct ipa_mhi_ch_alloc_resp_type_v01 { 660 uint8_t ch_id; 661 uint8_t is_success; 662 }; 663 struct ipa_mhi_alloc_channel_resp_msg_v01 { 664 struct ipa_qmi_response_type_v01 resp; 665 uint8_t alloc_resp_arr_valid; 666 uint32_t alloc_resp_arr_len; 667 struct ipa_mhi_ch_alloc_resp_type_v01 alloc_resp_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; 668 }; 669 #define IPA_MHI_ALLOC_CHANNEL_RESP_MSG_V01_MAX_MSG_LEN 23 670 enum ipa_clock_rate_enum_v01 { 671 IPA_CLOCK_RATE_ENUM_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 672 QMI_IPA_CLOCK_RATE_INVALID_V01 = 0, 673 QMI_IPA_CLOCK_RATE_LOW_SVS_V01 = 1, 674 QMI_IPA_CLOCK_RATE_SVS_V01 = 2, 675 QMI_IPA_CLOCK_RATE_NOMINAL_V01 = 3, 676 QMI_IPA_CLOCK_RATE_TURBO_V01 = 4, 677 IPA_CLOCK_RATE_ENUM_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 678 }; 679 struct ipa_mhi_clk_vote_req_msg_v01 { 680 uint8_t mhi_vote; 681 uint8_t tput_value_valid; 682 uint32_t tput_value; 683 uint8_t clk_rate_valid; 684 enum ipa_clock_rate_enum_v01 clk_rate; 685 }; 686 #define IPA_MHI_CLK_VOTE_REQ_MSG_V01_MAX_MSG_LEN 18 687 struct ipa_mhi_clk_vote_resp_msg_v01 { 688 struct ipa_qmi_response_type_v01 resp; 689 }; 690 #define IPA_MHI_CLK_VOTE_RESP_MSG_V01_MAX_MSG_LEN 7 691 struct ipa_mhi_cleanup_req_msg_v01 { 692 uint8_t cleanup_valid; 693 uint8_t cleanup; 694 }; 695 #define IPA_MHI_CLEANUP_REQ_MSG_V01_MAX_MSG_LEN 4 696 struct ipa_mhi_cleanup_resp_msg_v01 { 697 struct ipa_qmi_response_type_v01 resp; 698 }; 699 #define IPA_MHI_CLEANUP_RESP_MSG_V01_MAX_MSG_LEN 7 700 enum ipa_ep_desc_type_enum_v01 { 701 IPA_EP_DESC_TYPE_ENUM_MIN_VAL_V01 = IPA_INT_MIN, 702 DATA_EP_DESC_TYPE_RESERVED_V01 = 0x00, 703 DATA_EP_DESC_TYPE_EMB_CONS_V01 = 0x01, 704 DATA_EP_DESC_TYPE_EMB_PROD_V01 = 0x02, 705 DATA_EP_DESC_TYPE_RSC_PROD_V01 = 0x03, 706 DATA_EP_DESC_TYPE_QDSS_PROD_V01 = 0x04, 707 DATA_EP_DESC_TYPE_DPL_PROD_V01 = 0x05, 708 DATA_EP_DESC_TYPE_TETH_CONS_V01 = 0x06, 709 DATA_EP_DESC_TYPE_TETH_PROD_V01 = 0x07, 710 DATA_EP_DESC_TYPE_TETH_RMNET_CONS_V01 = 0x08, 711 DATA_EP_DESC_TYPE_TETH_RMNET_PROD_V01 = 0x09, 712 DATA_EP_DESC_TYPE_EMB_FLOW_CTL_CONS_V01 = 0x0A, 713 DATA_EP_DESC_TYPE_EMB_FLOW_CTL_PROD_V01 = 0x0B, 714 IPA_EP_DESC_TYPE_ENUM_MAX_VAL_V01 = IPA_INT_MAX, 715 }; 716 enum ipa_ic_type_enum_v01 { 717 IPA_IC_TYPE_ENUM_MIN_VAL_V01 = IPA_INT_MIN, 718 DATA_IC_TYPE_RESERVED_V01 = 0x00, 719 DATA_IC_TYPE_MHI_V01 = 0x01, 720 DATA_IC_TYPE_MHI_PRIME_V01 = 0x02, 721 DATA_IC_TYPE_USB_V01 = 0x03, 722 DATA_IC_TYPE_AP_V01 = 0x04, 723 DATA_IC_TYPE_Q6_V01 = 0x05, 724 DATA_IC_TYPE_UC_V01 = 0x06, 725 IPA_IC_TYPE_ENUM_MAX_VAL_V01 = IPA_INT_MAX, 726 }; 727 enum ipa_ep_status_type_v01 { 728 IPA_EP_STATUS_TYPE_MIN_VAL_V01 = IPA_INT_MIN, 729 DATA_EP_STATUS_RESERVED_V01 = 0x00, 730 DATA_EP_STATUS_STATIC_V01 = 0x01, 731 DATA_EP_STATUS_CONNECTED_V01 = 0x02, 732 DATA_EP_STATUS_DISCONNECTED_V01 = 0x03, 733 IPA_EP_STATUS_TYPE_MAX_VAL_V01 = IPA_INT_MAX, 734 }; 735 struct ipa_ep_id_type_v01 { 736 enum ipa_ic_type_enum_v01 ic_type; 737 enum ipa_ep_desc_type_enum_v01 ep_type; 738 uint32_t ep_id; 739 enum ipa_ep_status_type_v01 ep_status; 740 }; 741 struct ipa_endp_desc_indication_msg_v01 { 742 uint8_t ep_info_valid; 743 uint32_t ep_info_len; 744 struct ipa_ep_id_type_v01 ep_info[QMI_IPA_ENDP_DESC_NUM_MAX_V01]; 745 uint8_t num_eps_valid; 746 uint32_t num_eps; 747 }; 748 #define IPA_ENDP_DESC_INDICATION_MSG_V01_MAX_MSG_LEN 507 749 enum ipa_aggr_enum_type_v01 { 750 IPA_AGGR_ENUM_TYPE_MIN_VAL_V01 = IPA_INT_MIN, 751 DATA_AGGR_TYPE_RESERVED_V01 = 0x00, 752 DATA_AGGR_TYPE_QMAP_V01 = 0x01, 753 DATA_AGGR_TYPE_QMAPv5_V01 = 0x02, 754 DATA_AGGR_TYPE_INHERITED_V01 = 0x03, 755 IPA_AGGR_ENUM_TYPE_MAX_VAL_V01 = IPA_INT_MAX, 756 }; 757 struct ipa_mhi_prime_aggr_info_type_v01 { 758 enum ipa_ic_type_enum_v01 ic_type; 759 enum ipa_ep_desc_type_enum_v01 ep_type; 760 uint32_t bytes_count; 761 uint32_t pkt_count; 762 enum ipa_aggr_enum_type_v01 aggr_type; 763 }; 764 #define IPA_MHI_PRIME_AGGR_INFO_REQ_MSG_V01_MAX_MSG_LEN 631 765 struct ipa_mhi_prime_aggr_info_req_msg_v01 { 766 uint8_t aggr_info_valid; 767 uint32_t aggr_info_len; 768 struct ipa_mhi_prime_aggr_info_type_v01 aggr_info[QMI_IPA_ENDP_DESC_NUM_MAX_V01]; 769 uint8_t num_eps_valid; 770 uint32_t num_eps; 771 }; 772 #define IPA_MHI_PRIME_AGGR_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 773 struct ipa_mhi_prime_aggr_info_resp_msg_v01 { 774 struct ipa_qmi_response_type_v01 resp; 775 }; 776 struct ipa_add_offload_connection_req_msg_v01 { 777 uint8_t num_ipv4_filters_valid; 778 uint32_t num_ipv4_filters; 779 uint8_t num_ipv6_filters_valid; 780 uint32_t num_ipv6_filters; 781 uint8_t xlat_filter_indices_list_valid; 782 uint32_t xlat_filter_indices_list_len; 783 uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; 784 uint8_t filter_spec_ex2_list_valid; 785 uint32_t filter_spec_ex2_list_len; 786 struct ipa_filter_spec_ex2_type_v01 filter_spec_ex2_list[QMI_IPA_MAX_FILTERS_V01]; 787 uint8_t embedded_call_mux_id_valid; 788 uint32_t embedded_call_mux_id; 789 uint8_t default_mhi_path_valid; 790 uint8_t default_mhi_path; 791 }; 792 #define IPA_ADD_OFFLOAD_CONNECTION_REQ_MSG_V01_MAX_MSG_LEN 11361 793 struct ipa_add_offload_connection_resp_msg_v01 { 794 struct ipa_qmi_response_type_v01 resp; 795 uint8_t filter_handle_list_valid; 796 uint32_t filter_handle_list_len; 797 struct ipa_filter_rule_identifier_to_handle_map_v01 filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; 798 }; 799 #define IPA_ADD_OFFLOAD_CONNECTION_RESP_MSG_V01_MAX_MSG_LEN 523 800 struct ipa_remove_offload_connection_req_msg_v01 { 801 uint8_t filter_handle_list_valid; 802 uint32_t filter_handle_list_len; 803 struct ipa_filter_rule_identifier_to_handle_map_v01 filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; 804 uint8_t clean_all_rules_valid; 805 uint8_t clean_all_rules; 806 }; 807 #define IPA_REMOVE_OFFLOAD_CONNECTION_REQ_MSG_V01_MAX_MSG_LEN 520 808 struct ipa_remove_offload_connection_resp_msg_v01 { 809 uint8_t resp_valid; 810 struct ipa_qmi_response_type_v01 resp; 811 }; 812 #define IPA_REMOVE_OFFLOAD_CONNECTION_RESP_MSG_V01_MAX_MSG_LEN 7 813 struct ipa_bw_change_ind_msg_v01 { 814 uint8_t peak_bw_ul_valid; 815 uint32_t peak_bw_ul; 816 uint8_t peak_bw_dl_valid; 817 uint32_t peak_bw_dl; 818 }; 819 #define IPA_BW_CHANGE_IND_MSG_V01_MAX_MSG_LEN 14 820 #define QMI_IPA_INDICATION_REGISTER_REQ_V01 0x0020 821 #define QMI_IPA_INDICATION_REGISTER_RESP_V01 0x0020 822 #define QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 0x0021 823 #define QMI_IPA_INIT_MODEM_DRIVER_RESP_V01 0x0021 824 #define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01 0x0022 825 #define QMI_IPA_INSTALL_FILTER_RULE_REQ_V01 0x0023 826 #define QMI_IPA_INSTALL_FILTER_RULE_RESP_V01 0x0023 827 #define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01 0x0024 828 #define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01 0x0024 829 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0025 830 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0025 831 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0026 832 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0026 833 #define QMI_IPA_CONFIG_REQ_V01 0x0027 834 #define QMI_IPA_CONFIG_RESP_V01 0x0027 835 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0028 836 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0028 837 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0029 838 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0029 839 #define QMI_IPA_GET_DATA_STATS_REQ_V01 0x0030 840 #define QMI_IPA_GET_DATA_STATS_RESP_V01 0x0030 841 #define QMI_IPA_GET_APN_DATA_STATS_REQ_V01 0x0031 842 #define QMI_IPA_GET_APN_DATA_STATS_RESP_V01 0x0031 843 #define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01 0x0032 844 #define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 0x0032 845 #define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_V01 0x0033 846 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01 0x0034 847 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 0x0034 848 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01 0x0035 849 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01 0x0035 850 #define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01 0x0037 851 #define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_V01 0x0037 852 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01 0x0038 853 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_V01 0x0038 854 #define QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01 0x0039 855 #define QMI_IPA_GET_STATS_PER_CLIENT_RESP_V01 0x0039 856 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01 0x003A 857 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_V01 0x003A 858 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_V01 0x003A 859 #define QMI_IPA_MHI_CLK_VOTE_REQ_V01 0x003B 860 #define QMI_IPA_MHI_CLK_VOTE_RESP_V01 0x003B 861 #define QMI_IPA_MHI_READY_IND_V01 0x003C 862 #define QMI_IPA_MHI_ALLOC_CHANNEL_REQ_V01 0x003D 863 #define QMI_IPA_MHI_ALLOC_CHANNEL_RESP_V01 0x003D 864 #define QMI_IPA_MHI_CLEANUP_REQ_V01 0x003E 865 #define QMI_IPA_MHI_CLEANUP_RESP_V01 0x003E 866 #define QMI_IPA_ENDP_DESC_INDICATION_V01 0x003F 867 #define QMI_IPA_MHI_PRIME_AGGR_INFO_REQ_V01 0x0040 868 #define QMI_IPA_MHI_PRIME_AGGR_INFO_RESP_V01 0x0040 869 #define QMI_IPA_ADD_OFFLOAD_CONNECTION_REQ_V01 0x0041 870 #define QMI_IPA_ADD_OFFLOAD_CONNECTION_RESP_V01 0x0041 871 #define QMI_IPA_REMOVE_OFFLOAD_CONNECTION_REQ_V01 0x0042 872 #define QMI_IPA_REMOVE_OFFLOAD_CONNECTION_RESP_V01 0x0042 873 #define QMI_IPA_BW_CHANGE_INDICATION_V01 0x0044 874 #define QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01 162 875 #define QMI_IPA_INIT_MODEM_DRIVER_RESP_MAX_MSG_LEN_V01 25 876 #define QMI_IPA_INDICATION_REGISTER_REQ_MAX_MSG_LEN_V01 20 877 #define QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01 7 878 #define QMI_IPA_INSTALL_FILTER_RULE_REQ_MAX_MSG_LEN_V01 33705 879 #define QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01 783 880 #define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01 1899 881 #define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01 7 882 #define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01 7 883 #define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_MAX_MSG_LEN_V01 15 884 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 18 885 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 7 886 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 887 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 888 #define QMI_IPA_CONFIG_REQ_MAX_MSG_LEN_V01 102 889 #define QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01 7 890 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 18 891 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 892 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 7 893 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 894 #define QMI_IPA_GET_DATA_STATS_REQ_MAX_MSG_LEN_V01 11 895 #define QMI_IPA_GET_DATA_STATS_RESP_MAX_MSG_LEN_V01 2234 896 #define QMI_IPA_GET_APN_DATA_STATS_REQ_MAX_MSG_LEN_V01 36 897 #define QMI_IPA_GET_APN_DATA_STATS_RESP_MAX_MSG_LEN_V01 299 898 #define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 100 899 #define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 900 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 0 901 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 902 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_MAX_MSG_LEN_V01 4 903 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_MAX_MSG_LEN_V01 7 904 #define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_MAX_MSG_LEN_V01 34021 905 #define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_MAX_MSG_LEN_V01 523 906 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_MAX_MSG_LEN_V01 4 907 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_MAX_MSG_LEN_V01 7 908 #define QMI_IPA_GET_STATS_PER_CLIENT_REQ_MAX_MSG_LEN_V01 18 909 #define QMI_IPA_GET_STATS_PER_CLIENT_RESP_MAX_MSG_LEN_V01 3595 910 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_MAX_MSG_LEN_V01 9875 911 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_MAX_MSG_LEN_V01 7 912 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_MAX_MSG_LEN_V01 11 913 #define QMI_IPA_MAX_MSG_LEN 22685 914 #endif 915