1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #ifndef __MSM_DRM_H__ 26 #define __MSM_DRM_H__ 27 28 #include "drm.h" 29 #include "sde_drm.h" 30 31 #if defined(__cplusplus) 32 extern "C" { 33 #endif 34 35 /* Please note that modifications to all structs defined here are 36 * subject to backwards-compatibility constraints: 37 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit 38 * user/kernel compatibility 39 * 2) Keep fields aligned to their size 40 * 3) Because of how drm_ioctl() works, we can add new fields at 41 * the end of an ioctl if some care is taken: drm_ioctl() will 42 * zero out the new fields at the tail of the ioctl, so a zero 43 * value should have a backwards compatible meaning. And for 44 * output params, userspace won't see the newly added output 45 * fields.. so that has to be somehow ok. 46 */ 47 48 #define MSM_PIPE_NONE 0x00 49 #define MSM_PIPE_2D0 0x01 50 #define MSM_PIPE_2D1 0x02 51 #define MSM_PIPE_3D0 0x10 52 53 /* The pipe-id just uses the lower bits, so can be OR'd with flags in 54 * the upper 16 bits (which could be extended further, if needed, maybe 55 * we extend/overload the pipe-id some day to deal with multiple rings, 56 * but even then I don't think we need the full lower 16 bits). 57 */ 58 #define MSM_PIPE_ID_MASK 0xffff 59 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 60 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 61 62 /* timeouts are specified in clock-monotonic absolute times (to simplify 63 * restarting interrupted ioctls). The following struct is logically the 64 * same as 'struct timespec' but 32/64b ABI safe. 65 */ 66 struct drm_msm_timespec { 67 __s64 tv_sec; /* seconds */ 68 __s64 tv_nsec; /* nanoseconds */ 69 }; 70 71 /* 72 * HDR Metadata 73 * These are defined as per EDID spec and shall be used by the sink 74 * to set the HDR metadata for playback from userspace. 75 */ 76 77 #define HDR_PRIMARIES_COUNT 3 78 79 /* HDR EOTF */ 80 #define HDR_EOTF_SDR_LUM_RANGE 0x0 81 #define HDR_EOTF_HDR_LUM_RANGE 0x1 82 #define HDR_EOTF_SMTPE_ST2084 0x2 83 #define HDR_EOTF_HLG 0x3 84 85 #define DRM_MSM_EXT_HDR_METADATA 86 struct drm_msm_ext_hdr_metadata { 87 __u32 hdr_state; /* HDR state */ 88 __u32 eotf; /* electro optical transfer function */ 89 __u32 hdr_supported; /* HDR supported */ 90 __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; /* Primaries x */ 91 __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; /* Primaries y */ 92 __u32 white_point_x; /* white_point_x */ 93 __u32 white_point_y; /* white_point_y */ 94 __u32 max_luminance; /* Max luminance */ 95 __u32 min_luminance; /* Min Luminance */ 96 __u32 max_content_light_level; /* max content light level */ 97 __u32 max_average_light_level; /* max average light level */ 98 }; 99 100 /** 101 * HDR sink properties 102 * These are defined as per EDID spec and shall be used by the userspace 103 * to determine the HDR properties to be set to the sink. 104 */ 105 #define DRM_MSM_EXT_HDR_PROPERTIES 106 struct drm_msm_ext_hdr_properties { 107 __u8 hdr_metadata_type_one; /* static metadata type one */ 108 __u32 hdr_supported; /* HDR supported */ 109 __u32 hdr_eotf; /* electro optical transfer function */ 110 __u32 hdr_max_luminance; /* Max luminance */ 111 __u32 hdr_avg_luminance; /* Avg luminance */ 112 __u32 hdr_min_luminance; /* Min Luminance */ 113 }; 114 115 #define MSM_PARAM_GPU_ID 0x01 116 #define MSM_PARAM_GMEM_SIZE 0x02 117 #define MSM_PARAM_CHIP_ID 0x03 118 #define MSM_PARAM_MAX_FREQ 0x04 119 #define MSM_PARAM_TIMESTAMP 0x05 120 #define MSM_PARAM_GMEM_BASE 0x06 121 122 struct drm_msm_param { 123 __u32 pipe; /* in, MSM_PIPE_x */ 124 __u32 param; /* in, MSM_PARAM_x */ 125 __u64 value; /* out (get_param) or in (set_param) */ 126 }; 127 128 /* 129 * GEM buffers: 130 */ 131 132 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ 133 #define MSM_BO_GPU_READONLY 0x00000002 134 #define MSM_BO_CACHE_MASK 0x000f0000 135 /* cache modes */ 136 #define MSM_BO_CACHED 0x00010000 137 #define MSM_BO_WC 0x00020000 138 #define MSM_BO_UNCACHED 0x00040000 139 140 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 141 MSM_BO_GPU_READONLY | \ 142 MSM_BO_CACHED | \ 143 MSM_BO_WC | \ 144 MSM_BO_UNCACHED) 145 146 struct drm_msm_gem_new { 147 __u64 size; /* in */ 148 __u32 flags; /* in, mask of MSM_BO_x */ 149 __u32 handle; /* out */ 150 }; 151 152 #define MSM_INFO_IOVA 0x01 153 154 #define MSM_INFO_FLAGS (MSM_INFO_IOVA) 155 156 struct drm_msm_gem_info { 157 __u32 handle; /* in */ 158 __u32 flags; /* in - combination of MSM_INFO_* flags */ 159 __u64 offset; /* out, mmap() offset or iova */ 160 }; 161 162 #define MSM_PREP_READ 0x01 163 #define MSM_PREP_WRITE 0x02 164 #define MSM_PREP_NOSYNC 0x04 165 166 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 167 168 struct drm_msm_gem_cpu_prep { 169 __u32 handle; /* in */ 170 __u32 op; /* in, mask of MSM_PREP_x */ 171 struct drm_msm_timespec timeout; /* in */ 172 }; 173 174 struct drm_msm_gem_cpu_fini { 175 __u32 handle; /* in */ 176 }; 177 178 /* 179 * Cmdstream Submission: 180 */ 181 182 /* The value written into the cmdstream is logically: 183 * 184 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or 185 * 186 * When we have GPU's w/ >32bit ptrs, it should be possible to deal 187 * with this by emit'ing two reloc entries with appropriate shift 188 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. 189 * 190 * NOTE that reloc's must be sorted by order of increasing submit_offset, 191 * otherwise EINVAL. 192 */ 193 struct drm_msm_gem_submit_reloc { 194 __u32 submit_offset; /* in, offset from submit_bo */ 195 #ifdef __cplusplus 196 __u32 or_val; 197 #else 198 __u32 or; /* in, value OR'd with result */ 199 #endif 200 __s32 shift; /* in, amount of left shift (can be negative) */ 201 __u32 reloc_idx; /* in, index of reloc_bo buffer */ 202 __u64 reloc_offset; /* in, offset from start of reloc_bo */ 203 }; 204 205 /* submit-types: 206 * BUF - this cmd buffer is executed normally. 207 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are 208 * processed normally, but the kernel does not setup an IB to 209 * this buffer in the first-level ringbuffer 210 * CTX_RESTORE_BUF - only executed if there has been a GPU context 211 * switch since the last SUBMIT ioctl 212 */ 213 #define MSM_SUBMIT_CMD_BUF 0x0001 214 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 215 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 216 struct drm_msm_gem_submit_cmd { 217 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ 218 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ 219 __u32 submit_offset; /* in, offset into submit_bo */ 220 __u32 size; /* in, cmdstream size */ 221 __u32 pad; 222 __u32 nr_relocs; /* in, number of submit_reloc's */ 223 __u64 relocs; /* in, ptr to array of submit_reloc's */ 224 }; 225 226 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the 227 * cmdstream buffer(s) themselves or reloc entries) has one (and only 228 * one) entry in the submit->bos[] table. 229 * 230 * As a optimization, the current buffer (gpu virtual address) can be 231 * passed back through the 'presumed' field. If on a subsequent reloc, 232 * userspace passes back a 'presumed' address that is still valid, 233 * then patching the cmdstream for this entry is skipped. This can 234 * avoid kernel needing to map/access the cmdstream bo in the common 235 * case. 236 */ 237 #define MSM_SUBMIT_BO_READ 0x0001 238 #define MSM_SUBMIT_BO_WRITE 0x0002 239 240 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 241 242 struct drm_msm_gem_submit_bo { 243 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ 244 __u32 handle; /* in, GEM handle */ 245 __u64 presumed; /* in/out, presumed buffer address */ 246 }; 247 248 /* Valid submit ioctl flags: */ 249 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ 250 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ 251 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ 252 #define MSM_SUBMIT_FLAGS ( \ 253 MSM_SUBMIT_NO_IMPLICIT | \ 254 MSM_SUBMIT_FENCE_FD_IN | \ 255 MSM_SUBMIT_FENCE_FD_OUT | \ 256 0) 257 258 /* Each cmdstream submit consists of a table of buffers involved, and 259 * one or more cmdstream buffers. This allows for conditional execution 260 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 261 */ 262 struct drm_msm_gem_submit { 263 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ 264 __u32 fence; /* out */ 265 __u32 nr_bos; /* in, number of submit_bo's */ 266 __u32 nr_cmds; /* in, number of submit_cmd's */ 267 __u64 bos; /* in, ptr to array of submit_bo's */ 268 __u64 cmds; /* in, ptr to array of submit_cmd's */ 269 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ 270 }; 271 272 /* The normal way to synchronize with the GPU is just to CPU_PREP on 273 * a buffer if you need to access it from the CPU (other cmdstream 274 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 275 * handle the required synchronization under the hood). This ioctl 276 * mainly just exists as a way to implement the gallium pipe_fence 277 * APIs without requiring a dummy bo to synchronize on. 278 */ 279 struct drm_msm_wait_fence { 280 __u32 fence; /* in */ 281 __u32 pad; 282 struct drm_msm_timespec timeout; /* in */ 283 }; 284 285 /* madvise provides a way to tell the kernel in case a buffers contents 286 * can be discarded under memory pressure, which is useful for userspace 287 * bo cache where we want to optimistically hold on to buffer allocate 288 * and potential mmap, but allow the pages to be discarded under memory 289 * pressure. 290 * 291 * Typical usage would involve madvise(DONTNEED) when buffer enters BO 292 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. 293 * In the WILLNEED case, 'retained' indicates to userspace whether the 294 * backing pages still exist. 295 */ 296 #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ 297 #define MSM_MADV_DONTNEED 1 /* backing pages not needed */ 298 #define __MSM_MADV_PURGED 2 /* internal state */ 299 300 struct drm_msm_gem_madvise { 301 __u32 handle; /* in, GEM handle */ 302 __u32 madv; /* in, MSM_MADV_x */ 303 __u32 retained; /* out, whether backing store still exists */ 304 }; 305 306 /* HDR WRGB x and y index */ 307 #define DISPLAY_PRIMARIES_WX 0 308 #define DISPLAY_PRIMARIES_WY 1 309 #define DISPLAY_PRIMARIES_RX 2 310 #define DISPLAY_PRIMARIES_RY 3 311 #define DISPLAY_PRIMARIES_GX 4 312 #define DISPLAY_PRIMARIES_GY 5 313 #define DISPLAY_PRIMARIES_BX 6 314 #define DISPLAY_PRIMARIES_BY 7 315 #define DISPLAY_PRIMARIES_MAX 8 316 317 struct drm_panel_hdr_properties { 318 __u32 hdr_enabled; 319 320 /* WRGB X and y values arrayed in format */ 321 /* [WX, WY, RX, RY, GX, GY, BX, BY] */ 322 __u32 display_primaries[DISPLAY_PRIMARIES_MAX]; 323 324 /* peak brightness supported by panel */ 325 __u32 peak_brightness; 326 /* Blackness level supported by panel */ 327 __u32 blackness_level; 328 }; 329 330 /** 331 * struct drm_msm_event_req - Payload to event enable/disable ioctls. 332 * @object_id: DRM object id. e.g.: for crtc pass crtc id. 333 * @object_type: DRM object type. e.g.: for crtc set it to DRM_MODE_OBJECT_CRTC. 334 * @event: Event for which notification is being enabled/disabled. 335 * e.g.: for Histogram set - DRM_EVENT_HISTOGRAM. 336 * @client_context: Opaque pointer that will be returned during event response 337 * notification. 338 * @index: Object index(e.g.: crtc index), optional for user-space to set. 339 * Driver will override value based on object_id and object_type. 340 */ 341 struct drm_msm_event_req { 342 __u32 object_id; 343 __u32 object_type; 344 __u32 event; 345 __u64 client_context; 346 __u32 index; 347 }; 348 349 /** 350 * struct drm_msm_event_resp - payload returned when read is called for 351 * custom notifications. 352 * @base: Event type and length of complete notification payload. 353 * @info: Contains information about DRM that which raised this event. 354 * @data: Custom payload that driver returns for event type. 355 * size of data = base.length - (sizeof(base) + sizeof(info)) 356 */ 357 struct drm_msm_event_resp { 358 struct drm_event base; 359 struct drm_msm_event_req info; 360 __u8 data[]; 361 }; 362 363 /** 364 * struct drm_msm_power_ctrl: Payload to enable/disable the power vote 365 * @enable: enable/disable the power vote 366 * @flags: operation control flags, for future use 367 */ 368 struct drm_msm_power_ctrl { 369 __u32 enable; 370 __u32 flags; 371 }; 372 373 #define DRM_MSM_GET_PARAM 0x00 374 /* placeholder: 375 #define DRM_MSM_SET_PARAM 0x01 376 */ 377 #define DRM_MSM_GEM_NEW 0x02 378 #define DRM_MSM_GEM_INFO 0x03 379 #define DRM_MSM_GEM_CPU_PREP 0x04 380 #define DRM_MSM_GEM_CPU_FINI 0x05 381 #define DRM_MSM_GEM_SUBMIT 0x06 382 #define DRM_MSM_WAIT_FENCE 0x07 383 #define DRM_MSM_GEM_MADVISE 0x08 384 385 #define DRM_SDE_WB_CONFIG 0x40 386 #define DRM_MSM_REGISTER_EVENT 0x41 387 #define DRM_MSM_DEREGISTER_EVENT 0x42 388 #define DRM_MSM_RMFB2 0x43 389 #define DRM_MSM_POWER_CTRL 0x44 390 391 /* sde custom events */ 392 #define DRM_EVENT_HISTOGRAM 0x80000000 393 #define DRM_EVENT_AD_BACKLIGHT 0x80000001 394 #define DRM_EVENT_CRTC_POWER 0x80000002 395 #define DRM_EVENT_SYS_BACKLIGHT 0x80000003 396 #define DRM_EVENT_SDE_POWER 0x80000004 397 #define DRM_EVENT_IDLE_NOTIFY 0x80000005 398 #define DRM_EVENT_PANEL_DEAD 0x80000006 /* ESD event */ 399 #define DRM_EVENT_SDE_HW_RECOVERY 0X80000007 400 401 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 402 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 403 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 404 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 405 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 406 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 407 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 408 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 409 #define DRM_IOCTL_SDE_WB_CONFIG \ 410 DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) 411 #define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ 412 DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) 413 #define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ 414 DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) 415 #define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + \ 416 DRM_MSM_RMFB2), unsigned int) 417 #define DRM_IOCTL_MSM_POWER_CTRL DRM_IOW((DRM_COMMAND_BASE + \ 418 DRM_MSM_POWER_CTRL), struct drm_msm_power_ctrl) 419 420 #if defined(__cplusplus) 421 } 422 #endif 423 424 #endif /* __MSM_DRM_H__ */ 425