1//===-- X86InstrSVM.td - SVM Instruction Set Extension -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the instructions that make up the AMD SVM instruction 11// set. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// SVM instructions 17 18let SchedRW = [WriteSystem] in { 19// 0F 01 D9 20def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB; 21 22// 0F 01 DC 23def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB; 24 25// 0F 01 DD 26def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB; 27 28// 0F 01 DE 29let Uses = [EAX] in 30def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB; 31 32// 0F 01 D8 33let Uses = [EAX] in 34def VMRUN32 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%eax|eax}", []>, TB, 35 Requires<[Not64BitMode]>; 36let Uses = [RAX] in 37def VMRUN64 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%rax|rax}", []>, TB, 38 Requires<[In64BitMode]>; 39 40// 0F 01 DA 41let Uses = [EAX] in 42def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%eax|eax}", []>, TB, 43 Requires<[Not64BitMode]>; 44let Uses = [RAX] in 45def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%rax|rax}", []>, TB, 46 Requires<[In64BitMode]>; 47 48// 0F 01 DB 49let Uses = [EAX] in 50def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%eax|eax}", []>, TB, 51 Requires<[Not64BitMode]>; 52let Uses = [RAX] in 53def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%rax|rax}", []>, TB, 54 Requires<[In64BitMode]>; 55 56// 0F 01 DF 57let Uses = [EAX, ECX] in 58def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins), 59 "invlpga\t{%eax, %ecx|eax, ecx}", []>, TB, Requires<[Not64BitMode]>; 60let Uses = [RAX, ECX] in 61def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins), 62 "invlpga\t{%rax, %ecx|rax, ecx}", []>, TB, Requires<[In64BitMode]>; 63} // SchedRW 64