1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32I %s 4; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV32IA %s 6 7define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { 8; RV32I-LABEL: atomic_load_i8_unordered: 9; RV32I: # %bb.0: 10; RV32I-NEXT: addi sp, sp, -16 11; RV32I-NEXT: sw ra, 12(sp) 12; RV32I-NEXT: mv a1, zero 13; RV32I-NEXT: call __atomic_load_1 14; RV32I-NEXT: lw ra, 12(sp) 15; RV32I-NEXT: addi sp, sp, 16 16; RV32I-NEXT: ret 17; 18; RV32IA-LABEL: atomic_load_i8_unordered: 19; RV32IA: # %bb.0: 20; RV32IA-NEXT: lb a0, 0(a0) 21; RV32IA-NEXT: ret 22 %1 = load atomic i8, i8* %a unordered, align 1 23 ret i8 %1 24} 25 26define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { 27; RV32I-LABEL: atomic_load_i8_monotonic: 28; RV32I: # %bb.0: 29; RV32I-NEXT: addi sp, sp, -16 30; RV32I-NEXT: sw ra, 12(sp) 31; RV32I-NEXT: mv a1, zero 32; RV32I-NEXT: call __atomic_load_1 33; RV32I-NEXT: lw ra, 12(sp) 34; RV32I-NEXT: addi sp, sp, 16 35; RV32I-NEXT: ret 36; 37; RV32IA-LABEL: atomic_load_i8_monotonic: 38; RV32IA: # %bb.0: 39; RV32IA-NEXT: lb a0, 0(a0) 40; RV32IA-NEXT: ret 41 %1 = load atomic i8, i8* %a monotonic, align 1 42 ret i8 %1 43} 44 45define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { 46; RV32I-LABEL: atomic_load_i8_acquire: 47; RV32I: # %bb.0: 48; RV32I-NEXT: addi sp, sp, -16 49; RV32I-NEXT: sw ra, 12(sp) 50; RV32I-NEXT: addi a1, zero, 2 51; RV32I-NEXT: call __atomic_load_1 52; RV32I-NEXT: lw ra, 12(sp) 53; RV32I-NEXT: addi sp, sp, 16 54; RV32I-NEXT: ret 55; 56; RV32IA-LABEL: atomic_load_i8_acquire: 57; RV32IA: # %bb.0: 58; RV32IA-NEXT: lb a0, 0(a0) 59; RV32IA-NEXT: fence r, rw 60; RV32IA-NEXT: ret 61 %1 = load atomic i8, i8* %a acquire, align 1 62 ret i8 %1 63} 64 65define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { 66; RV32I-LABEL: atomic_load_i8_seq_cst: 67; RV32I: # %bb.0: 68; RV32I-NEXT: addi sp, sp, -16 69; RV32I-NEXT: sw ra, 12(sp) 70; RV32I-NEXT: addi a1, zero, 5 71; RV32I-NEXT: call __atomic_load_1 72; RV32I-NEXT: lw ra, 12(sp) 73; RV32I-NEXT: addi sp, sp, 16 74; RV32I-NEXT: ret 75; 76; RV32IA-LABEL: atomic_load_i8_seq_cst: 77; RV32IA: # %bb.0: 78; RV32IA-NEXT: fence rw, rw 79; RV32IA-NEXT: lb a0, 0(a0) 80; RV32IA-NEXT: fence r, rw 81; RV32IA-NEXT: ret 82 %1 = load atomic i8, i8* %a seq_cst, align 1 83 ret i8 %1 84} 85 86define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { 87; RV32I-LABEL: atomic_load_i16_unordered: 88; RV32I: # %bb.0: 89; RV32I-NEXT: addi sp, sp, -16 90; RV32I-NEXT: sw ra, 12(sp) 91; RV32I-NEXT: mv a1, zero 92; RV32I-NEXT: call __atomic_load_2 93; RV32I-NEXT: lw ra, 12(sp) 94; RV32I-NEXT: addi sp, sp, 16 95; RV32I-NEXT: ret 96; 97; RV32IA-LABEL: atomic_load_i16_unordered: 98; RV32IA: # %bb.0: 99; RV32IA-NEXT: lh a0, 0(a0) 100; RV32IA-NEXT: ret 101 %1 = load atomic i16, i16* %a unordered, align 2 102 ret i16 %1 103} 104 105define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { 106; RV32I-LABEL: atomic_load_i16_monotonic: 107; RV32I: # %bb.0: 108; RV32I-NEXT: addi sp, sp, -16 109; RV32I-NEXT: sw ra, 12(sp) 110; RV32I-NEXT: mv a1, zero 111; RV32I-NEXT: call __atomic_load_2 112; RV32I-NEXT: lw ra, 12(sp) 113; RV32I-NEXT: addi sp, sp, 16 114; RV32I-NEXT: ret 115; 116; RV32IA-LABEL: atomic_load_i16_monotonic: 117; RV32IA: # %bb.0: 118; RV32IA-NEXT: lh a0, 0(a0) 119; RV32IA-NEXT: ret 120 %1 = load atomic i16, i16* %a monotonic, align 2 121 ret i16 %1 122} 123 124define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { 125; RV32I-LABEL: atomic_load_i16_acquire: 126; RV32I: # %bb.0: 127; RV32I-NEXT: addi sp, sp, -16 128; RV32I-NEXT: sw ra, 12(sp) 129; RV32I-NEXT: addi a1, zero, 2 130; RV32I-NEXT: call __atomic_load_2 131; RV32I-NEXT: lw ra, 12(sp) 132; RV32I-NEXT: addi sp, sp, 16 133; RV32I-NEXT: ret 134; 135; RV32IA-LABEL: atomic_load_i16_acquire: 136; RV32IA: # %bb.0: 137; RV32IA-NEXT: lh a0, 0(a0) 138; RV32IA-NEXT: fence r, rw 139; RV32IA-NEXT: ret 140 %1 = load atomic i16, i16* %a acquire, align 2 141 ret i16 %1 142} 143 144define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { 145; RV32I-LABEL: atomic_load_i16_seq_cst: 146; RV32I: # %bb.0: 147; RV32I-NEXT: addi sp, sp, -16 148; RV32I-NEXT: sw ra, 12(sp) 149; RV32I-NEXT: addi a1, zero, 5 150; RV32I-NEXT: call __atomic_load_2 151; RV32I-NEXT: lw ra, 12(sp) 152; RV32I-NEXT: addi sp, sp, 16 153; RV32I-NEXT: ret 154; 155; RV32IA-LABEL: atomic_load_i16_seq_cst: 156; RV32IA: # %bb.0: 157; RV32IA-NEXT: fence rw, rw 158; RV32IA-NEXT: lh a0, 0(a0) 159; RV32IA-NEXT: fence r, rw 160; RV32IA-NEXT: ret 161 %1 = load atomic i16, i16* %a seq_cst, align 2 162 ret i16 %1 163} 164 165define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { 166; RV32I-LABEL: atomic_load_i32_unordered: 167; RV32I: # %bb.0: 168; RV32I-NEXT: addi sp, sp, -16 169; RV32I-NEXT: sw ra, 12(sp) 170; RV32I-NEXT: mv a1, zero 171; RV32I-NEXT: call __atomic_load_4 172; RV32I-NEXT: lw ra, 12(sp) 173; RV32I-NEXT: addi sp, sp, 16 174; RV32I-NEXT: ret 175; 176; RV32IA-LABEL: atomic_load_i32_unordered: 177; RV32IA: # %bb.0: 178; RV32IA-NEXT: lw a0, 0(a0) 179; RV32IA-NEXT: ret 180 %1 = load atomic i32, i32* %a unordered, align 4 181 ret i32 %1 182} 183 184define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { 185; RV32I-LABEL: atomic_load_i32_monotonic: 186; RV32I: # %bb.0: 187; RV32I-NEXT: addi sp, sp, -16 188; RV32I-NEXT: sw ra, 12(sp) 189; RV32I-NEXT: mv a1, zero 190; RV32I-NEXT: call __atomic_load_4 191; RV32I-NEXT: lw ra, 12(sp) 192; RV32I-NEXT: addi sp, sp, 16 193; RV32I-NEXT: ret 194; 195; RV32IA-LABEL: atomic_load_i32_monotonic: 196; RV32IA: # %bb.0: 197; RV32IA-NEXT: lw a0, 0(a0) 198; RV32IA-NEXT: ret 199 %1 = load atomic i32, i32* %a monotonic, align 4 200 ret i32 %1 201} 202 203define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { 204; RV32I-LABEL: atomic_load_i32_acquire: 205; RV32I: # %bb.0: 206; RV32I-NEXT: addi sp, sp, -16 207; RV32I-NEXT: sw ra, 12(sp) 208; RV32I-NEXT: addi a1, zero, 2 209; RV32I-NEXT: call __atomic_load_4 210; RV32I-NEXT: lw ra, 12(sp) 211; RV32I-NEXT: addi sp, sp, 16 212; RV32I-NEXT: ret 213; 214; RV32IA-LABEL: atomic_load_i32_acquire: 215; RV32IA: # %bb.0: 216; RV32IA-NEXT: lw a0, 0(a0) 217; RV32IA-NEXT: fence r, rw 218; RV32IA-NEXT: ret 219 %1 = load atomic i32, i32* %a acquire, align 4 220 ret i32 %1 221} 222 223define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { 224; RV32I-LABEL: atomic_load_i32_seq_cst: 225; RV32I: # %bb.0: 226; RV32I-NEXT: addi sp, sp, -16 227; RV32I-NEXT: sw ra, 12(sp) 228; RV32I-NEXT: addi a1, zero, 5 229; RV32I-NEXT: call __atomic_load_4 230; RV32I-NEXT: lw ra, 12(sp) 231; RV32I-NEXT: addi sp, sp, 16 232; RV32I-NEXT: ret 233; 234; RV32IA-LABEL: atomic_load_i32_seq_cst: 235; RV32IA: # %bb.0: 236; RV32IA-NEXT: fence rw, rw 237; RV32IA-NEXT: lw a0, 0(a0) 238; RV32IA-NEXT: fence r, rw 239; RV32IA-NEXT: ret 240 %1 = load atomic i32, i32* %a seq_cst, align 4 241 ret i32 %1 242} 243 244define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { 245; RV32I-LABEL: atomic_load_i64_unordered: 246; RV32I: # %bb.0: 247; RV32I-NEXT: addi sp, sp, -16 248; RV32I-NEXT: sw ra, 12(sp) 249; RV32I-NEXT: mv a1, zero 250; RV32I-NEXT: call __atomic_load_8 251; RV32I-NEXT: lw ra, 12(sp) 252; RV32I-NEXT: addi sp, sp, 16 253; RV32I-NEXT: ret 254; 255; RV32IA-LABEL: atomic_load_i64_unordered: 256; RV32IA: # %bb.0: 257; RV32IA-NEXT: addi sp, sp, -16 258; RV32IA-NEXT: sw ra, 12(sp) 259; RV32IA-NEXT: mv a1, zero 260; RV32IA-NEXT: call __atomic_load_8 261; RV32IA-NEXT: lw ra, 12(sp) 262; RV32IA-NEXT: addi sp, sp, 16 263; RV32IA-NEXT: ret 264 %1 = load atomic i64, i64* %a unordered, align 8 265 ret i64 %1 266} 267 268define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { 269; RV32I-LABEL: atomic_load_i64_monotonic: 270; RV32I: # %bb.0: 271; RV32I-NEXT: addi sp, sp, -16 272; RV32I-NEXT: sw ra, 12(sp) 273; RV32I-NEXT: mv a1, zero 274; RV32I-NEXT: call __atomic_load_8 275; RV32I-NEXT: lw ra, 12(sp) 276; RV32I-NEXT: addi sp, sp, 16 277; RV32I-NEXT: ret 278; 279; RV32IA-LABEL: atomic_load_i64_monotonic: 280; RV32IA: # %bb.0: 281; RV32IA-NEXT: addi sp, sp, -16 282; RV32IA-NEXT: sw ra, 12(sp) 283; RV32IA-NEXT: mv a1, zero 284; RV32IA-NEXT: call __atomic_load_8 285; RV32IA-NEXT: lw ra, 12(sp) 286; RV32IA-NEXT: addi sp, sp, 16 287; RV32IA-NEXT: ret 288 %1 = load atomic i64, i64* %a monotonic, align 8 289 ret i64 %1 290} 291 292define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { 293; RV32I-LABEL: atomic_load_i64_acquire: 294; RV32I: # %bb.0: 295; RV32I-NEXT: addi sp, sp, -16 296; RV32I-NEXT: sw ra, 12(sp) 297; RV32I-NEXT: addi a1, zero, 2 298; RV32I-NEXT: call __atomic_load_8 299; RV32I-NEXT: lw ra, 12(sp) 300; RV32I-NEXT: addi sp, sp, 16 301; RV32I-NEXT: ret 302; 303; RV32IA-LABEL: atomic_load_i64_acquire: 304; RV32IA: # %bb.0: 305; RV32IA-NEXT: addi sp, sp, -16 306; RV32IA-NEXT: sw ra, 12(sp) 307; RV32IA-NEXT: addi a1, zero, 2 308; RV32IA-NEXT: call __atomic_load_8 309; RV32IA-NEXT: lw ra, 12(sp) 310; RV32IA-NEXT: addi sp, sp, 16 311; RV32IA-NEXT: ret 312 %1 = load atomic i64, i64* %a acquire, align 8 313 ret i64 %1 314} 315 316define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { 317; RV32I-LABEL: atomic_load_i64_seq_cst: 318; RV32I: # %bb.0: 319; RV32I-NEXT: addi sp, sp, -16 320; RV32I-NEXT: sw ra, 12(sp) 321; RV32I-NEXT: addi a1, zero, 5 322; RV32I-NEXT: call __atomic_load_8 323; RV32I-NEXT: lw ra, 12(sp) 324; RV32I-NEXT: addi sp, sp, 16 325; RV32I-NEXT: ret 326; 327; RV32IA-LABEL: atomic_load_i64_seq_cst: 328; RV32IA: # %bb.0: 329; RV32IA-NEXT: addi sp, sp, -16 330; RV32IA-NEXT: sw ra, 12(sp) 331; RV32IA-NEXT: addi a1, zero, 5 332; RV32IA-NEXT: call __atomic_load_8 333; RV32IA-NEXT: lw ra, 12(sp) 334; RV32IA-NEXT: addi sp, sp, 16 335; RV32IA-NEXT: ret 336 %1 = load atomic i64, i64* %a seq_cst, align 8 337 ret i64 %1 338} 339 340define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind { 341; RV32I-LABEL: atomic_store_i8_unordered: 342; RV32I: # %bb.0: 343; RV32I-NEXT: addi sp, sp, -16 344; RV32I-NEXT: sw ra, 12(sp) 345; RV32I-NEXT: mv a2, zero 346; RV32I-NEXT: call __atomic_store_1 347; RV32I-NEXT: lw ra, 12(sp) 348; RV32I-NEXT: addi sp, sp, 16 349; RV32I-NEXT: ret 350; 351; RV32IA-LABEL: atomic_store_i8_unordered: 352; RV32IA: # %bb.0: 353; RV32IA-NEXT: sb a0, 0(a1) 354; RV32IA-NEXT: ret 355 store atomic i8 %b, i8* %a unordered, align 1 356 ret void 357} 358 359define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind { 360; RV32I-LABEL: atomic_store_i8_monotonic: 361; RV32I: # %bb.0: 362; RV32I-NEXT: addi sp, sp, -16 363; RV32I-NEXT: sw ra, 12(sp) 364; RV32I-NEXT: mv a2, zero 365; RV32I-NEXT: call __atomic_store_1 366; RV32I-NEXT: lw ra, 12(sp) 367; RV32I-NEXT: addi sp, sp, 16 368; RV32I-NEXT: ret 369; 370; RV32IA-LABEL: atomic_store_i8_monotonic: 371; RV32IA: # %bb.0: 372; RV32IA-NEXT: sb a0, 0(a1) 373; RV32IA-NEXT: ret 374 store atomic i8 %b, i8* %a monotonic, align 1 375 ret void 376} 377 378define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind { 379; RV32I-LABEL: atomic_store_i8_release: 380; RV32I: # %bb.0: 381; RV32I-NEXT: addi sp, sp, -16 382; RV32I-NEXT: sw ra, 12(sp) 383; RV32I-NEXT: addi a2, zero, 3 384; RV32I-NEXT: call __atomic_store_1 385; RV32I-NEXT: lw ra, 12(sp) 386; RV32I-NEXT: addi sp, sp, 16 387; RV32I-NEXT: ret 388; 389; RV32IA-LABEL: atomic_store_i8_release: 390; RV32IA: # %bb.0: 391; RV32IA-NEXT: fence rw, w 392; RV32IA-NEXT: sb a0, 0(a1) 393; RV32IA-NEXT: ret 394 store atomic i8 %b, i8* %a release, align 1 395 ret void 396} 397 398define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind { 399; RV32I-LABEL: atomic_store_i8_seq_cst: 400; RV32I: # %bb.0: 401; RV32I-NEXT: addi sp, sp, -16 402; RV32I-NEXT: sw ra, 12(sp) 403; RV32I-NEXT: addi a2, zero, 5 404; RV32I-NEXT: call __atomic_store_1 405; RV32I-NEXT: lw ra, 12(sp) 406; RV32I-NEXT: addi sp, sp, 16 407; RV32I-NEXT: ret 408; 409; RV32IA-LABEL: atomic_store_i8_seq_cst: 410; RV32IA: # %bb.0: 411; RV32IA-NEXT: fence rw, w 412; RV32IA-NEXT: sb a0, 0(a1) 413; RV32IA-NEXT: ret 414 store atomic i8 %b, i8* %a seq_cst, align 1 415 ret void 416} 417 418define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind { 419; RV32I-LABEL: atomic_store_i16_unordered: 420; RV32I: # %bb.0: 421; RV32I-NEXT: addi sp, sp, -16 422; RV32I-NEXT: sw ra, 12(sp) 423; RV32I-NEXT: mv a2, zero 424; RV32I-NEXT: call __atomic_store_2 425; RV32I-NEXT: lw ra, 12(sp) 426; RV32I-NEXT: addi sp, sp, 16 427; RV32I-NEXT: ret 428; 429; RV32IA-LABEL: atomic_store_i16_unordered: 430; RV32IA: # %bb.0: 431; RV32IA-NEXT: sh a0, 0(a1) 432; RV32IA-NEXT: ret 433 store atomic i16 %b, i16* %a unordered, align 2 434 ret void 435} 436 437define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind { 438; RV32I-LABEL: atomic_store_i16_monotonic: 439; RV32I: # %bb.0: 440; RV32I-NEXT: addi sp, sp, -16 441; RV32I-NEXT: sw ra, 12(sp) 442; RV32I-NEXT: mv a2, zero 443; RV32I-NEXT: call __atomic_store_2 444; RV32I-NEXT: lw ra, 12(sp) 445; RV32I-NEXT: addi sp, sp, 16 446; RV32I-NEXT: ret 447; 448; RV32IA-LABEL: atomic_store_i16_monotonic: 449; RV32IA: # %bb.0: 450; RV32IA-NEXT: sh a0, 0(a1) 451; RV32IA-NEXT: ret 452 store atomic i16 %b, i16* %a monotonic, align 2 453 ret void 454} 455 456define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind { 457; RV32I-LABEL: atomic_store_i16_release: 458; RV32I: # %bb.0: 459; RV32I-NEXT: addi sp, sp, -16 460; RV32I-NEXT: sw ra, 12(sp) 461; RV32I-NEXT: addi a2, zero, 3 462; RV32I-NEXT: call __atomic_store_2 463; RV32I-NEXT: lw ra, 12(sp) 464; RV32I-NEXT: addi sp, sp, 16 465; RV32I-NEXT: ret 466; 467; RV32IA-LABEL: atomic_store_i16_release: 468; RV32IA: # %bb.0: 469; RV32IA-NEXT: fence rw, w 470; RV32IA-NEXT: sh a0, 0(a1) 471; RV32IA-NEXT: ret 472 store atomic i16 %b, i16* %a release, align 2 473 ret void 474} 475 476define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind { 477; RV32I-LABEL: atomic_store_i16_seq_cst: 478; RV32I: # %bb.0: 479; RV32I-NEXT: addi sp, sp, -16 480; RV32I-NEXT: sw ra, 12(sp) 481; RV32I-NEXT: addi a2, zero, 5 482; RV32I-NEXT: call __atomic_store_2 483; RV32I-NEXT: lw ra, 12(sp) 484; RV32I-NEXT: addi sp, sp, 16 485; RV32I-NEXT: ret 486; 487; RV32IA-LABEL: atomic_store_i16_seq_cst: 488; RV32IA: # %bb.0: 489; RV32IA-NEXT: fence rw, w 490; RV32IA-NEXT: sh a0, 0(a1) 491; RV32IA-NEXT: ret 492 store atomic i16 %b, i16* %a seq_cst, align 2 493 ret void 494} 495 496define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind { 497; RV32I-LABEL: atomic_store_i32_unordered: 498; RV32I: # %bb.0: 499; RV32I-NEXT: addi sp, sp, -16 500; RV32I-NEXT: sw ra, 12(sp) 501; RV32I-NEXT: mv a2, zero 502; RV32I-NEXT: call __atomic_store_4 503; RV32I-NEXT: lw ra, 12(sp) 504; RV32I-NEXT: addi sp, sp, 16 505; RV32I-NEXT: ret 506; 507; RV32IA-LABEL: atomic_store_i32_unordered: 508; RV32IA: # %bb.0: 509; RV32IA-NEXT: sw a0, 0(a1) 510; RV32IA-NEXT: ret 511 store atomic i32 %b, i32* %a unordered, align 4 512 ret void 513} 514 515define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind { 516; RV32I-LABEL: atomic_store_i32_monotonic: 517; RV32I: # %bb.0: 518; RV32I-NEXT: addi sp, sp, -16 519; RV32I-NEXT: sw ra, 12(sp) 520; RV32I-NEXT: mv a2, zero 521; RV32I-NEXT: call __atomic_store_4 522; RV32I-NEXT: lw ra, 12(sp) 523; RV32I-NEXT: addi sp, sp, 16 524; RV32I-NEXT: ret 525; 526; RV32IA-LABEL: atomic_store_i32_monotonic: 527; RV32IA: # %bb.0: 528; RV32IA-NEXT: sw a0, 0(a1) 529; RV32IA-NEXT: ret 530 store atomic i32 %b, i32* %a monotonic, align 4 531 ret void 532} 533 534define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind { 535; RV32I-LABEL: atomic_store_i32_release: 536; RV32I: # %bb.0: 537; RV32I-NEXT: addi sp, sp, -16 538; RV32I-NEXT: sw ra, 12(sp) 539; RV32I-NEXT: addi a2, zero, 3 540; RV32I-NEXT: call __atomic_store_4 541; RV32I-NEXT: lw ra, 12(sp) 542; RV32I-NEXT: addi sp, sp, 16 543; RV32I-NEXT: ret 544; 545; RV32IA-LABEL: atomic_store_i32_release: 546; RV32IA: # %bb.0: 547; RV32IA-NEXT: fence rw, w 548; RV32IA-NEXT: sw a0, 0(a1) 549; RV32IA-NEXT: ret 550 store atomic i32 %b, i32* %a release, align 4 551 ret void 552} 553 554define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind { 555; RV32I-LABEL: atomic_store_i32_seq_cst: 556; RV32I: # %bb.0: 557; RV32I-NEXT: addi sp, sp, -16 558; RV32I-NEXT: sw ra, 12(sp) 559; RV32I-NEXT: addi a2, zero, 5 560; RV32I-NEXT: call __atomic_store_4 561; RV32I-NEXT: lw ra, 12(sp) 562; RV32I-NEXT: addi sp, sp, 16 563; RV32I-NEXT: ret 564; 565; RV32IA-LABEL: atomic_store_i32_seq_cst: 566; RV32IA: # %bb.0: 567; RV32IA-NEXT: fence rw, w 568; RV32IA-NEXT: sw a0, 0(a1) 569; RV32IA-NEXT: ret 570 store atomic i32 %b, i32* %a seq_cst, align 4 571 ret void 572} 573 574define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind { 575; RV32I-LABEL: atomic_store_i64_unordered: 576; RV32I: # %bb.0: 577; RV32I-NEXT: addi sp, sp, -16 578; RV32I-NEXT: sw ra, 12(sp) 579; RV32I-NEXT: mv a3, zero 580; RV32I-NEXT: call __atomic_store_8 581; RV32I-NEXT: lw ra, 12(sp) 582; RV32I-NEXT: addi sp, sp, 16 583; RV32I-NEXT: ret 584; 585; RV32IA-LABEL: atomic_store_i64_unordered: 586; RV32IA: # %bb.0: 587; RV32IA-NEXT: addi sp, sp, -16 588; RV32IA-NEXT: sw ra, 12(sp) 589; RV32IA-NEXT: mv a3, zero 590; RV32IA-NEXT: call __atomic_store_8 591; RV32IA-NEXT: lw ra, 12(sp) 592; RV32IA-NEXT: addi sp, sp, 16 593; RV32IA-NEXT: ret 594 store atomic i64 %b, i64* %a unordered, align 8 595 ret void 596} 597 598define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind { 599; RV32I-LABEL: atomic_store_i64_monotonic: 600; RV32I: # %bb.0: 601; RV32I-NEXT: addi sp, sp, -16 602; RV32I-NEXT: sw ra, 12(sp) 603; RV32I-NEXT: mv a3, zero 604; RV32I-NEXT: call __atomic_store_8 605; RV32I-NEXT: lw ra, 12(sp) 606; RV32I-NEXT: addi sp, sp, 16 607; RV32I-NEXT: ret 608; 609; RV32IA-LABEL: atomic_store_i64_monotonic: 610; RV32IA: # %bb.0: 611; RV32IA-NEXT: addi sp, sp, -16 612; RV32IA-NEXT: sw ra, 12(sp) 613; RV32IA-NEXT: mv a3, zero 614; RV32IA-NEXT: call __atomic_store_8 615; RV32IA-NEXT: lw ra, 12(sp) 616; RV32IA-NEXT: addi sp, sp, 16 617; RV32IA-NEXT: ret 618 store atomic i64 %b, i64* %a monotonic, align 8 619 ret void 620} 621 622define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind { 623; RV32I-LABEL: atomic_store_i64_release: 624; RV32I: # %bb.0: 625; RV32I-NEXT: addi sp, sp, -16 626; RV32I-NEXT: sw ra, 12(sp) 627; RV32I-NEXT: addi a3, zero, 3 628; RV32I-NEXT: call __atomic_store_8 629; RV32I-NEXT: lw ra, 12(sp) 630; RV32I-NEXT: addi sp, sp, 16 631; RV32I-NEXT: ret 632; 633; RV32IA-LABEL: atomic_store_i64_release: 634; RV32IA: # %bb.0: 635; RV32IA-NEXT: addi sp, sp, -16 636; RV32IA-NEXT: sw ra, 12(sp) 637; RV32IA-NEXT: addi a3, zero, 3 638; RV32IA-NEXT: call __atomic_store_8 639; RV32IA-NEXT: lw ra, 12(sp) 640; RV32IA-NEXT: addi sp, sp, 16 641; RV32IA-NEXT: ret 642 store atomic i64 %b, i64* %a release, align 8 643 ret void 644} 645 646define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind { 647; RV32I-LABEL: atomic_store_i64_seq_cst: 648; RV32I: # %bb.0: 649; RV32I-NEXT: addi sp, sp, -16 650; RV32I-NEXT: sw ra, 12(sp) 651; RV32I-NEXT: addi a3, zero, 5 652; RV32I-NEXT: call __atomic_store_8 653; RV32I-NEXT: lw ra, 12(sp) 654; RV32I-NEXT: addi sp, sp, 16 655; RV32I-NEXT: ret 656; 657; RV32IA-LABEL: atomic_store_i64_seq_cst: 658; RV32IA: # %bb.0: 659; RV32IA-NEXT: addi sp, sp, -16 660; RV32IA-NEXT: sw ra, 12(sp) 661; RV32IA-NEXT: addi a3, zero, 5 662; RV32IA-NEXT: call __atomic_store_8 663; RV32IA-NEXT: lw ra, 12(sp) 664; RV32IA-NEXT: addi sp, sp, 16 665; RV32IA-NEXT: ret 666 store atomic i64 %b, i64* %a seq_cst, align 8 667 ret void 668} 669